NXP Semiconductors UM11227 - Port a Pin Pull Enable Register (PTAPE); Port a Data Direction Register (PTADD)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Table 25. PTAD register field descriptions
Field Description
4
PTAD[4:0]
PTAD[4:0] – For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are
configured as outputs, reads return the last value written to this register. Writes are latched into all bits of
this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding
MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset
also configures all port pins as high-impedance inputs with pullups disabled.
Each bit 0 = pin inactive or connected to ground; Result of Reset
Each bit 1 = pin active or connected to V
DD(A)
0 0 0 0 0 = Result of Reset
10.12.1.3 Port A pin pull enable register (PTAPE)
Table 26. Port A pin pull enable register (PTAPE) (address $0001)
Bit 7 6 5 4 3 2 1 0
R 0 0 0 0
W — — — —
PTAPE3 PTAPE2 PTAPE1 PTAPE0
Reset ($00) 0 0 0 0 0 0 0 0
Table 27. PTAPE register field descriptions
Field Description
3:0
PTAPE
PTAPE[3:0] – Each bit selects the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured or default as output, these bits have no effect and the internal pullup devices are
disabled.
Each bit 0 = Internal pullup device disabled for port A bit n; Result of Reset
Each bit 1 = Internal pullup device enabled for port A bit n.
0 0 0 0 = Result of Reset
10.12.1.4 Port A data direction register (PTADD)
Table 28. Port A data direction register (PTADD) (address $0003)
Bit 7 6 5 4 3 2 1 0
R 0 0 0 1
W — — — —
PTADD3 PTADD2 PTADD1 PTADD0
Reset ($00) 0 0 0 0 0 0 0 0
Table 29. PTADD register field descriptions
Field Description
3:0
PTADD[3:0]
PTADD[3:0] - Each bit selects the direction of port A pins and what is read for PTADD reads.
Each bit 0 = Input (output driver disabled) and reads return the pin value; Result of Reset
Each bit 1 = Output driver enabled for port A bit n and PTADD reads return the contents of PTADDn.
0 0 0 0 = Result of Reset
Note: In GPIO mode, PTA4 operates as output-only.