NXP Semiconductors UM11227 - Register Definition; BDC Registers and Control Bits; BDC Status and Control Register (BDCSCR)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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9.3 Register definition
This section contains the descriptions of the BDC registers and control bits.
This section refers to registers and control bits only by their names. A NXP-provided
equate or header file is used to translate these names into the appropriate absolute
addresses.
9.3.1 BDC registers and control bits
The BDC has two registers:
• The BDC status and control register (BDCSCR) is an 8-bit register containing control
and status bits for the BACKGROUND DEBUG controller.
• The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match
address.
These registers are accessed with dedicated serial BDC commands and are not located
in the memory space of the target MCU (so they do not have addresses and cannot be
accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be
read or written at any time. For example, the ENBDM control bit may not be written while
the MCU is in ACTIVE BACKGROUND mode. (This prevents the ambiguous condition
of the control bit forbidding ACTIVE BACKGROUND mode while the MCU is already in
ACTIVE BACKGROUND mode.) Also, the four status bits (BDMACT, WS, WSF, and
DVF) are read-only status indicators and can never be written by the WRITE_CONTROL
serial BDC command. The clock switch (CLKSW) control bit may be read or written at
any time.
9.3.2 BDC status and control register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and
WRITE_CONTROL) but is not accessible to user programs because it is not located in
the normal memory map of the MCU.
Table 11. BDC status and control register (BDCSCR)
Bit 7 6 5 4 3 2 1 0
R BDMACT WS WSF DVF
W
ENBDM
reserved
BKPTEN FTS CLKSW
reserved reserved reserved
Normal Reset 0 0 0 0 0 0 0 0
Reset in Active BDM 1 1 0 0 1 0 0 0
Table 12. BDCSCR register field descriptions
Field Description
7
ENBDM
Enable BDM (Permit ACTIVE BACKGROUND Mode) — Typically, this bit is written to 1 by the debug host
shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1
until a normal reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow ACTIVE BACKGROUND mode commands