NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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POR = true power-on reset result, after the power has been applied.
Other resets = the result of resets that occur while power remains applied, such
as low-power-mode exits, low-voltage detection, illegal operations,
enabling a function block, etc.
U = the state of the bit remains unaffected by the type of reset mentioned
in the leftmost column.
Read function = the functional name of a readable bit within the register, appearing in
the columns to the right
Write function = the functional name of a writable bit within the register, appearing in
the columns to the right
RW function = the functional name of a bit that is both readable and writable
— = a readable bit that is not writable, meaning writes to the bit will have
no reaction.
rwm = a read/write bit modified by hardware in some fashion other than by a
reset.
slfclr = a self-clearing bit; writing a one has an effect, but the bit always reads
as a zero.
w1c = a write-once-to-clear bit; a status bit that can be read, and is cleared
by a writing a one.
0 or 1 = the result of a read, write, or reset; 0 meaning clear(ed) / de-
asserted / de-activated; 1 meaning set / asserted / activated.
10.2 Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an
interrupt service routine (ISR), and then restore the CPU status so processing resumes
where it left off before the interrupt. Other than the software interrupt (SWI), which is a
program instruction, interrupts are caused by hardware events. The debug module can
also generate an SWI under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag
will become set. The CPU will not respond until and unless the local interrupt enable is a
logic 1 to enable the interrupt. The I bit in the CCR must be a logic 0 to allow interrupts.
The global interrupt mask (I bit) in the CCR is initially set after reset which masks
(prevents) all maskable interrupt sources. The user program initializes the stack pointer
and performs other system setup before clearing the I bit to allow the CPU to respond to
interrupts. When the CPU receives a qualified interrupt request, it completes the current
instruction before responding to the interrupt. The interrupt sequence follows the same
cycle-by-cycle sequence as the SWI instruction and consists of:
• Saving the CPU registers on the stack
• Setting the I bit in the CCR to mask further interrupts
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending
• Filling the instruction queue with the first three bytes of program information starting
from the address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid
the possibility of another interrupt interrupting the ISR itself (this is called nesting of
interrupts). Normally, the I bit is restored to 0 when the CCR is restored from the value
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