NXP Semiconductors UM11227 - Vector Summary; Interrupt Service Routines

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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10.2.2 Vector summary
Table 17 provides a summary of all interrupt sources. Higher-priority sources are located
toward the bottom of the table (at the higher vector addresses). All of these vectors are
a 2-byte address that the firmware uses as the destination address. This allows the
firmware to intercept all vectors and add additional processing as needed. The additional
process latency for each interrupt is described in the corresponding firmware user guide.
Therefore, the high-order byte of the address for the user’s interrupt service routine is
located at the lower address in the vector address column, and the low-order byte of
the address for the interrupt service routine is located at the higher address. When an
interrupt condition occurs, an associated flag bit becomes set. If the associated local
interrupt enable is set, an interrupt request is sent to the CPU. Within the CPU, if the
global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction,
stack the PCL, PCH, X, A, and CCR CPU registers, set the I bit, and then fetch the
interrupt vector for the highest priority pending interrupt. Processing then continues in the
interrupt service routine.
The triggering of any of these vector fetches wakes the MCU from any of the STOP
modes.
10.3 Interrupt service routines
Interrupt service routines are managed by NXP firmware unless erased and overwritten
by customer applications. This section describes the management of hardware vectors to
user application vectors.
Each hardware vector is accessed when the prioritized interrupt is recognized. An
interrupt service routine (ISR) clears the interrupt and sets appropriate flags for the
user to poll, and, when appropriate, jumps to the assigned user vector as described in
Table 17.
Table 17. Interrupt service routines
Vector
priority
Hardware
address
Vector
name
Module
source
Flag
name
Enable
name
Description
15 $FFE0 - $FFE1 vkbi KBI KBF KBIE Keyboard pin edge / level applied
14 $FFE2 - $FFE3 Vfrc FRC FRCF_IF FRC_
COMP_
EN
Free running counter timer and comparison
matched.
13 $FFE4 - $FFE5 — — — — not assigned
12 $FFE6 - $FFE7 Vrti PMC RTIF RTIE Real-time interrupt timer expiration if not in Stop
1
11 $FFE8 - $FFE9 Vlfrcvr LFR LFIDF
LFCDF
LFERF
LFDRF
LFIDE
LFCDIE
LFERIE
LFDRIE
LF receiver valid ID reception in data mode
LF receiver carrier detection in carrier mode
LF receiver error detection in Manchester
decode mode
LF receiver 8-bits data received in Manchester
decode mode
10 $FFEA - $FFEB Vadc ADC COCO AIEN ADC conversion completed
9 $FFEC - $FFED Vrf RFM RFIF
RFEF
RFVF
RFIEN RF transmitter x-bits data transmitted
RF transmitter error detection
RF transmitter low voltage detection