NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
183 / 205
The FRC_EN_HALT and FRC_CLR bits are operated in a mutually exclusive manner,
such that halting the FRC will not occur while the FRC_CLR bit is 1, and conversely
clearing the FRC will not be attempted while the FRC_EN_HALT is 0.
When the FRC is enabled and running, the user application may clear the count value of
FRCTIMERH/L to $0000 by writing 1 to the FRC_CLR bit. The FRC_CLR bit should not
be written to 1 while the FRC_EN_HALT is 0.
Note that an expected result of clearing the FRC, followed by reading the FRCTIMERH/L
may not return exactly $0000 due to the asynchronous nature of the LFO as clock.
The lower address of the FRC compare register holds the new FRC_COMP[15:8] bits.
Then next address holds the FRC_COMP[7:0] bits. The new control and status bits
FRC_COMP_EN, FRC_COMP_IACK, and FRC_IF reside in the same register as the
existing FRC control bits.
Reset disables the comparison function, i.e. force FRC_COMP_EN, FRC_COMP_IACK,
and FRC_IF each to 0, and forces FRC_COMP[15:0] to default value of $FFFF in order
to minimize the probability of an instantaneous interrupt upon enabling.
Operation of the comparison interrupt function follows the operation of the FRC in test
mode, i.e. if clocked by HFO (default 64 × MFO) in test mode, the comparison interrupt
event will be faster than if clocked by the LFO in user mode.
10.25.2 Free running counter register descriptions
10.25.2.1 FRC status and control register (FRCCR)
Table 201. FRC status and control register (FRCCR) (address $1880)
Bit 7 6 5 4 3 2 1 0
R 0 0 0 FRC_IF 0 0
W FRC_CLR —
FRC_
EN_HALT
FRC_
COMP_EN
FRC_
COMP_
IACK
— — —
Reset 0 0 U 0 0 U 0 0
POR ($00) 0 0 0 0 0 0 0 0
Table 202. FRCCR register field descriptions
Field Description
7
FRC_CLR
FRC_CLR – Free Running Counter Clear
The write-only FRC_CLR bit is used to clear the free running counter.
0 = No effect; Result of Reset
1 = clear the counter to $0000
5
FRC_
EN_HALT
FRC_EN_HALT — Free Running Counter Enable Bit
This bit reads the FRC_EN_HOLD signal from FRC analog.
0 = disable and halt the counter; Result of power-on reset. Existing state remains under all other types of
reset.
1 = enable and release the counter
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