NXP Semiconductors UM11227 - Tab. 85. LF Received Data Register (LFDATA) (Address $0025); Tab. 86. LFDATA Register Field Descriptions; Tab. 87. LF Receiver ID Register (LFID) (Address $0026); 6 LF Received Data Register (LFDATA)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
99 / 205
Field Description
0
LFIAK
LFIAK – LF Interrupt Acknowledge Control
Writing a one to the LFIAK bit clears the LFDRF, LFERF, LFCDF, LFIDF, LFOVF and LFEOMF flag bits.
When a one is written to the LFIAK, it is automatically cleared at the next positive edge of the MCU bus
clock. Then, reading the LFIAK bit is allowed but will always return zero. Writing a zero the LFIAK bit has no
effect.
0 = No effect; Result of power-on reset. Existing state remains after all other reset types.
1 = Write 1 to clear the LFDRF, LFERF, LFCDF, LFIDF, LFOVF and LFEOMF flag bits.
10.15.17.6 LF received data register (LFDATA)
Table 85. LF received data register (LFDATA) (address $0025)
Bit 7 6 5 4 3 2 1 0
R LFRXD7 LFRXD6 LFRXD5 LFRXD4 LFRXD3 LFRXD2 LFRXD1 LFRXD0
W — — — — — — — —
Reset ($) U U U U U U U U
POR ($00) 0 0 0 0 0 0 0 0
LFR soft
reset ($00)
0 0 0 0 0 0 0 0
Table 86. LFDATA register field descriptions
Field Description
7:0
LFDATA
The LFDATA[7:0] is a read-only register that contains the most recent received data value. As data is
serially received by the LFR, it is assembled into 8-bit values. When a new complete 8-bit value is received,
it is moved into the LFDATA register, over-writing any previous value, and the LFDRF data ready flag is set
to indicate a value is available for the MCU to read. If a previous value was ready but was not read out of
the LFDATA register before a new data byte is ready, the LFOVF overflow flag is also set to indicate this
overflow condition. Writes to LFDATA have no meaning or effect.
$00 = Result of power on or LFR reset. Existing state remains after all other reset types.
10.15.17.7 LF receiver ID registers (LFID)
Table 87. LF receiver ID register (LFID) (address $0026)
Bit 7 6 5 4 3 2 1 0
R
W
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Reset U U U U U U U U
POR ($00) 0 0 0 0 0 0 0 0
LFR soft
reset ($00)
0 0 0 0 0 0 0 0