NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
148 / 205
Field Description
5:4
SSEL[1:0]
SSEL[1:0] – Sensor Selection
The two bits SSEL[1:0] control which channel of the C-V multiplexer will be selected for conversion by the
ADC block.
0 0 = P-cell selected; Result of Reset
0 1 = G-cell South or 1 selected
1 0 = G-cell North or 0 selected
1 1 = PRT option selected
Note: Refer to the NTM88 specific data sheet for the available configuration by part number.
3
SPAR_ERR
SPAR_ERR – SMI Parity Error
The SPAR_ERR bit indicates if a parity error has been detected. As a result, the ADC reading will be exactly
or near 0x0000 when a parity error has occurred. To become aware of the error, the user application should
check the SPAR_ERR flag, whenever the SMI returns values that are near or exactly 0x0000.
0 = no parity error detected; Result of Reset
1 = parity error detected
10.19.2.3 SMI configuration register (SMICFG)
Table 150. SMI configuration register (SMICFG) (address $0042)
Bit 7 6 5 4 3 2 1 0
R 0 0 0
W
ITRIG ITIG_EN
— — —
FILEN FILT1 FILT0
Reset ($00) 0 0 0 0 0 0 0 0
Table 151. SMICFG register field descriptions
Field Description
7
ITRIG
ITRIG — Interval Trigger (write-only)
The ITRIG bit triggers interval timing to commence when in Low Power Direct Mode, provided the Interval
Trigger feature is enabled. When this bit is set, it is automatically cleared.
0 = No effect; Result of Reset
1 = Commence interval timing
6
ITRIGEN
ITRIGEN — Interval Trigger Enable (write-only)
The ITRIGEN bit enables interval trigger functionality.
0 = Interval trigger disabled; Result of Reset
1 = Interval trigger enabled
2
FILEN
FILEN – Filter Enable
The FILEN bit enables or disables the low-pass filter block:
0 = low-pass filter bypassed; Result of Reset
1 = low-pass filter enabled
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