NXP Semiconductors UM11227 - Tab. 94. LF Receiver Control C Register (LFCTRLC) (Address $002 A); Tab. 95. LFCTRLC Register Field Descriptions; LF Receiver Control C Register (LFCTRLC)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Field Description
2
ONMODE
ONMODE – On Behavior Mode Control
This read/write bit selects how an error will affect the ON time.
0 = Any error will stop the ON time; Result of power on or LFR reset. Existing state remains after all other
reset types.
1 = If remaining ON time, the LFR will go back to sniff mode at any error - recommended setting.
1:0
CHK125[1:0]
CHK125[1:0] – Carrier Check
The two bits CHK125[1:0] control the CARVAL carrier validation frequency checking method.
0 0 = the carrier is validated on n x (2 x 32 µs packets), where n is depending on the LFCDTM value –
recommended setting for Low Sensitivity mode
0 1 = the carrier is validated on n x (8 x 8 µs packets), where n is depending on the LFCDTM value –
recommended setting for High Sensitivity mode; Result of power on or LFR reset. Existing state remains
after all other reset types.
1 0 = same performance as 0 1
1 1 = same performance as 0 0
10.15.17.10 LF receiver control C register (LFCTRLC)
Table 94. LF receiver control C register (LFCTRLC) (address $002A)
Bit 7 6 5 4 3 2 1 0
R
W
AMPGAIN1 AMPGAIN0 FINSEL1 FINSEL0 AZEN LOWQ1 LOWQ0 DEQEN
Reset ($) U U U U U U U U
POR ($C8) 1 1 0 0 1 0 0 0
LFR soft
reset ($C8)
1 1 0 0 1 0 0 0
Table 95. LFCTRLC register field descriptions
Field Description
7:6
AMPG
AIN[1:0]
AMPGAIN[1:0] – Third stage Amplifier Gain Control
These bits control the third amplifier gain.
0 0 = Gain of ~2.2 - recommended setting
0 1 = Gain of ~3.8
1 0 = Gain of ~4.9
1 1 = Gain of ~6.6; Result of power on or LFR reset. Existing state remains after all other reset types.
5:4
FINSEL[1:0]
FINSEL[1:0] – Final stage Amplifier Gain Control
These bits select the final stage of the LOGAMP.
0 0 = Continuous time biasing - Fixed Gain 6; Result of power on or LFR reset. Existing state remains after
all other reset types.
0 1 = Continuous time biasing - Programmable Gain - recommended setting
1 0 = Fourth rectifier disabled
1 1 = Fourth rectifier disabled
3
AZEN
AZEN – Data Auto Zero Enable
This bit allows the AZ sequence during data frame.
0 = AZ during data disabled; Result of power on or LFR reset. Existing state remains after all other reset
types.
1 = AZ during data enabled - recommended setting