NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Table 23. Truth table for pullup and pulldown resistors
PTAPE[3:0]
pull enable
PTADD[3:0]
data direction
KBIPE[3:0]
KBI pin enable
KBEDG[3:0]
KBI edge select
Pullup Pulldown
0 0 x x disabled disabled
1 0 0 x enabled disabled
x 1 0 x disabled disabled
1 0 1 0 enabled disabled
1 0 1 1 disabled enabled
PTBPE[1:0]
pull enable
PTBADD[1:0]
data direction
0 0 disabled x
1 0 enabled x
x 1 disabled x
Port A 0 supports an external interrupt as a peripheral function. The PTA0 GPIO can be
configured as an external Interrupt Request (IRQ), which when activated will force the
CPU to exit a stop mode.
Port A 4 supports a background developer interface as a peripheral function. The PTA4
GPIO can be configured as the BDM serial data interface (BKGD) by an external host
holding the PTA4 pin low prior to POR release.
10.12.1.1 General Purpose I/O
This section explains software controls related to general purpose input/output (I/O) and
pin control. The NTM88 has seven general-purpose I/O pins which are comprised of a
general use 5-bit port A and a 2-bit port B.
To avoid extra current drain from floating input pins, the user’s application software
must configure these pins so that they do not float (see Section 10.12.1.1.1 "Unused pin
configuration").
Reading and writing of general purpose I/O is performed through the port data registers.
The direction, either input or output, is controlled through the port data direction registers.
The general purpose I/O port function for an individual pin is illustrated in the block
diagram in Figure 13.
The data direction control bit (PTxDDn) determines whether the output buffer for the
associated pin is enabled, and also controls the source for port data register reads. The
input buffer for the associated pin is always enabled unless the pin is enabled as an
analog function.
When a shared digital function is enabled for a pin, the output buffer is controlled by the
shared function. However, the data direction register bit still controls the source for reads
of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers
are disabled. A value of 0 is read for any port data bit where the bit is an input (PTxDDn
= 0) and the input buffer is disabled. In general, whenever a pin is shared with both an
alternate digital function and an analog function, the analog function has priority such that
if both the digital and analog functions are enabled, the analog function controls the pin.
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