NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
9E63 6
COM
3 SP1
9ED3 5
CPX
4 SP2
9EE3 4
CPX
3 SP1
9EF3 6
CPHX
3 SP1
9E64 6
LSR
3 SP1
9ED4 5
AND
4 SP2
9EE4 4
AND
3 SP1
9ED5 5
BIT
4 SP2
9EE5 4
BIT
3 SP1
9E66 6
ROR
3 SP1
9ED6 5
LDA
4 SP2
9EE6 4
LDA
3 SP1
9E67 6
ASR
3 SP1
9ED7 5
STA
4 SP2
9EE7 4
STA
3 SP1
9E68 6
LSL
3 SP1
9ED8 5
EOR
4 SP2
9EE8 4
EOR
3 SP1
9E69 6
ROL
3 SP1
9ED9 5
ADC
4 SP2
9EE9 4
ADC
3 SP1
9E6A 6
DEC
3 SP1
9EDA 5
ORA
4 SP2
9EEA 4
ORA
3 SP1
9E6B 8
DBNZ
4 SP1
9EDB 5
ADD
4 SP2
9EEB 4
ADD
3 SP1
9E6C 6
INC
3 SP1
9E6D 5
TST
3 SP1
9EAE 5
LDHX
2 IX
9EBE 6
LDHX
4 IX2
9ECE 5
LDHX
3 IX1
9EDE 5
LDX
4 SP2
9EEE 4
LDX
3 SP1
9EFE 5
LDHX
3 SP1
9E6F 6
CLR
3 SP1
9EDF 5
STX
4 SP2
9EEF 4
STX
3 SP1
9EFF 5
STHX
3 SP1
INH Inherent REL relative SP1 Stack Pointer, 8-bit offset
IMM Immediate IX Indexed, no offset SP2 Stack Pointer, 16 bit offset
DIR Direct IX1 Indexed, 8-bit offset IX+ Indexed, No offset with post increment
EXT Extended IX2 Indexed, 16 bit offset IX1+ Indexed, 1 byte offset with post increment
DD DIR to DIR IMD IMM to DIR
IX+D IX+ to DIR DIX+ DIR to IX+
Note: All Sheet 2 Opcodes are preceded by the Page 2 Prebyte (9E)
Prebyte (9E) and Opcode in Hexadecimal
Number of Bytes
9E60 6
SUB
3 SP1
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
9 Development support
9.1 Introduction
This chapter describes the single-wire BACKGROUND DEBUG mode (BDM), which uses
the on-chip BACKGROUND DEBUG controller (BDC) module.
9.1.1 Features
Features of the BDC module include:
• Single pin for mode selection and background communications
• BDC registers are not located in the memory map
• SYNC command to determine target communications rate
• Non-intrusive commands for memory access
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