NXP Semiconductors UM11227 - Periodic Wake-Up Timer Module

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Table 61. TPMCyVH/L register field descriptions
Field Description
15:0
TPMCy
V[15:0]
The TPMCyV[15:0] read/write registers contain the captured TPM1 counter value of the input capture
function or the output compare value for the output compare or PWM functions. The channel value registers
are cleared by reset.
In input capture mode, reading either byte (TPM1CyVH or TPM1CyVL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPM1CySC register is written.
In output compare or PWM modes, writing to either byte (TPM1CyVH or TPM1CyVL) latches the value into
a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer
channel value registers.
This latching mechanism may be manually reset by writing to the TPM1CySC register. This latching
mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler
implementations.
$0000 = Result of Reset
10.14 Periodic wake-up timer module
The periodic wake-up timer (PWU) generates a periodic interrupt to wake up the MCU
from any of the STOP modes. It also has an optional periodic reset to restart the MCU.
It is driven by the LFO oscillator in the RTI module which generates a clock at a nominal
one millisecond interval. The LFO and the wake-up timer are always active and cannot
be powered off by any software control. The control bits are set so that there is either
a periodic wake-up, a periodic reset, or both a wake-up interrupt and a periodic reset.
No combination of control bits will disable both the wake-up interrupt and the periodic
reset. In addition, there is no hardware control that can mask a wake-up interrupt once it
is generated by the PWU.
aaa-031056
PROGRAMMABLE
PRESCALER
CONTROL
LOGIC
WAKEUP
DIVIDER
8-bit
LFO
WCLK
TRE
TRO
PRFAK
WUFAK
PRST
PRF
WUKI
WUF
PERIODIC
RESET
DIVIDER
8-bit
WUT[7:0]WDIV[7:0] PRST[7:0]
RCLK
Figure 18. Periodic wake-up timer block diagram