NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Field Description
4
FRC_
COMP_EN
FRC_COMP_EN – Enable of FRC comparison
When set to 1, the bit FRC_COMPEN will enable the FRC interrupt function.
0 = comparison interrupt disabled; Result of Reset
1 = comparison interrupt enabled
3
FRC_
COMP_IACK
FRC_COMP_IACK – FRC Comparison Interrupt Acknowledge
The write-only FRC_COMP_IACK bit is used to clear the free running counter interrupt.
0 = no effect; Result of Reset1 = clear the FRC interrupt
2
FRC_IF
FRC_IF – FRC Interrupt Flag
The FRC_IF bit indicates that the FRC interrupt is pending
0 = no FRC interrupt is pending; Result of Reset
1 = FRC interrupt is pending.
10.25.2.2 FRC timer high and low registers (FRCTIMERH/L)
Table 203. FRC timer high register (FRCTIMERH) (address $1881)
Bit 15 14 13 12 11 10 9 8
R
W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
POR ($00) 0 0 0 0 0 0 0 0
Other
resets
U U U U U U U U
Table 204. FRC timer low register (FRCTIMERL) (address $1882)
Bit 7 6 5 4 3 2 1 0
R
W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
POR ($00) 0 0 0 0 0 0 0 0
Other
resets
U U U U U U U U
Table 205. FRCTIMERH/L register field descriptions
Field Description
15:0
FRCTIM
ERH/L
The 16-bit FRC timer register holds the value of the free running count, which can be halted or restarted, or
reset to $0000.
$0000 = Result of Reset
10.25.2.3 FRC compare high and low registers (FRCCOMP2/1)
Table 206. FRC compare high register (FRCCOMP2) (address $1883)
Bit 15 14 13 12 11 10 9 8
R
W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8