NXP Semiconductors UM11227 - Tab. 123. PLLCR0; PLLCR1; PLLCR2; PLLCR3 Register Field Descriptions

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
124 / 205
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Table 123. PLLCR0 / PLLCR1 / PLLCR2 / PLLCR3 register field descriptions
Field Description
15:3
AFREQ[12:0]
The 13 bits AFREQ[12:0] control the FSK carriers for transmitting 0’s. The AFREQ[12:0] control bits are
cleared by the RFMRST signal.
Where:
f
XTAL
= External crystal frequency in Hz = typical 26 MHz
CF = state of the CF carrier select control bit.
AFREQ[12:0] = decimal value, 1 LSB of AFREQ = 3.17 kHz
$0000 = Result of Reset
2
POL
POL – Data Polarity
The POL control bit selects the polarity of the data encoding selected by the CODE[1:0] bits. The POL
control bit is cleared by the RFMRST signal.
0 = NRZ and MCU direct DATA bit data non-inverted and Manchester encoding polarity; Result of Reset
1 = all types of encoding polarity are inverted.
1:0
CODE[1:0]
CODE[1:0] – Data Encoding and Source
The two bits CODE[1:0] control bits select the type of data encoding and source of data for the RF output.
The CODE[1:0] control bits are cleared by the RFMRST signal.
0 0 = Manchester encoded data from the RFM data buffer; Result of Reset
0 1 = Bi-Phase encoded data from the RFM data buffer.
1 0 = NRZ encoded data from the RFM data buffer.
1 1 =MCU direct mode with RF output driven by the state of the DATA bit.
15:3
BFREQ[12:0]
The 13 bits BFREQ[12:0] control the OOK carrier for transmitting 1’s, where lack of carrier defines OOK 0’s.
Where:
f
XTAL
= External crystal frequency in Hz = typical 26 MHz
CF = state of the CF carrier select control bit.
BFREQ[12:0] = decimal value, 1 LSB of BFREQ = 3.17 kHz
$0000 = Result of Reset
2
CF
CF – Carrier Frequency Control
The CF control bit selects the optimal VCO setup and correct divider for the 500 kHz reference clock to the
MCU on DX based on the external crystals required for the desired carrier frequency. The CF control bit is
cleared by the RFMRST signal.
0 = Configured for 315 MHz, 12.1154 PLL divider using a 26.000 MHz external crystal; Result of Reset
1 = Configured for 434 MHz, 16.6923 PLL divider using a 26.000 MHz external crystal.