NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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8.4.4 Direct addressing mode (DIR)
In direct addressing mode, the instruction includes the low-order 8 bits of an address
in the direct page (0x0000–0x00FF). During execution, a 16-bit address is formed by
concatenating an implied 0x00 for the high-order half of the address and the direct
address from the instruction to get the 16-bit address where the desired operand is
located. DIR is faster and more memory efficient than specifying a complete 16-bit
address for the operand.
8.4.5 Extended addressing mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next
2 bytes of program memory after the opcode (high byte first).
8.4.6 Indexed addressing mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X
index register pair and two that use the stack pointer as the base reference.
8.4.6.1 Indexed, no offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
as the address of the operand needed to complete the instruction.
8.4.6.2 Indexed, no offset with post increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
as the address of the operand needed to complete the instruction. The index register
pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is only used for MOV and CBEQ instructions.
8.4.6.3 Indexed, 8-bit offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
plus an unsigned 8-bit offset included in the instruction as the address of the operand
needed to complete the instruction.
8.4.6.4 Indexed, 8-bit offset with post increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
plus an unsigned 8-bit offset included in the instruction as the address of the operand
needed to complete the instruction. The index register pair is then incremented (H:X =
H:X + 0x0001) after the operand has been fetched. This addressing mode is used only
for the CBEQ instruction.
8.4.6.5 Indexed, 16-bit offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
plus a 16-bit offset included in the instruction as the address of the operand needed to
complete the instruction.
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