NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
135 / 205
Table 137. ADRH/L register field descriptions
Field Description
11:0
ADRH/L
The 12-bit ADR[11:0] are 2 read-only CPU accessible registers to present data result values following ADC
conversions:
• ADRH – Data result high
• ADRL – data result low
A 12-bit data result register holds the final conversion result. The data captured in the result register is
driven from the SAR Block.
$0000 = Result of Reset
10.17.1.4 ADC compare value high and low registers (ADCVH/L)
Table 138. ADCV compare value high register (ADCVH) (address $0034)
Bit 7 6 5 4 3 2 1 0
R 0 0 0 0 ADCV11 ADCV10 ADCV9 ADCV8
W — — — — — — — —
Reset ($00) 0 0 0 0 0 0 0 0
Table 139. ADCV compare value low register (ADCVL) (address $0035)
Bit 7 6 5 4 3 2 1 0
R ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
W — — — — — — — —
Reset ($00) 0 0 0 0 0 0 0 0
Table 140. ADCVH/L register field descriptions
Field Description
11:0
ADCVH/L
The 12-bit compare value ADCV[11:0] is accessible through the ADCVH and ADCVL registers:
• ADCVH – Compare value high nibble
• ADCVL – Compare value low pair of nibbles
The ADCVH and ADCVL registers are standard read/write accessible. CPU writes to the 4 low-order bits of
ADCVH update reg_adcv[11:8] and writes to ADCVL update the 8 low-order bits (reg_adcv[7:0]). The ADCV
field is used as the referenced compare value on Compare type conversions (when ACFE = 1).
$0000 = Result of Reset
10.17.1.5 ADC configuration register
Table 141. ADC configuration register (address $0036)
Bit 7 6 5 4 3 2 1 0
R
W
ADLPC ADIV1 ADIV0 ADLSMP MODE1 MODE0 ADICLK1 ADICLK0
Reset ($00) 0 0 0 0 0 0 0 0
To Next Page
Loading...