NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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8.4.6.6 SP-Relative, 8-bit offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus
an unsigned 8-bit offset included in the instruction as the address of the operand needed
to complete the instruction.
8.4.6.7 SP-Relative, 16-bit offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a
16-bit offset included in the instruction as the address of the operand needed to complete
the instruction.
8.5 Special operations
The CPU performs a few special operations that are similar to instructions but do not
have opcodes like other CPU instructions. In addition, a few instructions such as STOP
and WAIT directly affect other MCU circuitry. This section provides additional information
about these operations.
8.5.1 Reset sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the
COP (computer operating properly) watchdog, or by assertion of an external active-low
reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing
(the MCU does not wait for an instruction boundary before responding to a reset event).
For a more detailed discussion about how the MCU recognizes resets and determines
the source, see Section 10.11 "Reset, interrupts and system configuration".
The reset event is considered concluded when the sequence to determine whether the
reset came from an internal source is done and when the reset pin is no longer asserted.
At the conclusion of a reset event, the CPU performs a 6-cycle sequence to fetch the
reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for
execution of the first program instruction.
8.5.2 Interrupt sequence
When an interrupt is requested, the CPU completes the current instruction before
responding to the interrupt. At this point, the program counter is pointing at the start of
the next instruction, which is where the CPU should return after servicing the interrupt.
The CPU responds to an interrupt by performing the same sequence of operations as
for a software interrupt (SWI) instruction, except the address used for the vector fetch is
determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch 3 bytes of program information, starting at the address indicated by the interrupt
vector, to fill the instruction queue in preparation for execution of the first instruction in
the interrupt service routine.
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