NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Clock cycle c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16
Bit assignment b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
T1 1 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 p1 p0
R0 r s4 s3 s2 s1 s0 r r r r r r r r p1 p0
T2 1 m m m m m d7 d6 d5 d4 d3 d2 d1 d0 p1 p0
R1 1 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 p1 p0
T3 t t t t t t t t t t t t t t p1 p0
Write byte to
Address
R2 1 s4 s3 s2 s1 s0 d7 d6 d5 d4 d3 d2 d1 d0 p1 p0
Where:
c1 – c16 = SCLK cycles 1 (b15) through 16 (b0), most significant bit first, least significant bit last
b15:0 = bit assignments for each clock cycle, b15 = 0 for read; b15 = 1 for write
a12:0 = 13 LSB’s of address being read or written; $0000 to $1FFF is direct; $C000 to $FFFF is indirect
p1:0 = “Even” parity bits, p1 calculated for contents of b15:9; p0 calculated for contents of b8:2
s4:0 = slave status:
0 0 0 0 0 = all OK, no need for re-try.
1 x x x x = reserved for future fault modes, default to 0 until defined
x 1 x x x =
the response in R0 for first T1 input after reset
in the case of commands ignored by SPI due to error in previous read command; i.e. invalid data in response
in the case the write command did not execute
x x 1 x x = clock fault, not enough clocks or too many clocks per SS_B cycle
x x x 1 x = parity fault from either p1 or p0
x x x x 1 = internal bus contention fault, SPI does not gain access to peripheral bus in the prescribed time, or attempt
access illegal or security-blocked address
d7:0 = data being read or written
t = contents of next master transmission T#+1
m = master stuff bits, 0 or 1 by master choice, and included as part of parity calculation
r = contents of previous slave response R#-1
10.18.2 SPI signal timing definition
aaa-031062
DSP Out
SS_B
t
LEAD
t
SCLKR
t
SCLK
t
SCLKF
t
SCLKH
t
SSCLK
t
SS_REJ
t
CLKSS
t
DISABLE
t
HOLD_OUT
t
VALID
t
SCLKL
t
ACCESS
t
SETUP
t
HOLD_IN
t
LAG
t
SSN
SCLK
MISO
MOSI
Figure 43. SPI signal timing diagram
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