NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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tool to determine the correct clock frequency for BACKGROUND DEBUG serial
communications.
BDC serial communications use a custom serial protocol first introduced on the
M68HC12 Family of microcontrollers. This protocol assumes the host knows the
communication clock rate that is determined by the target BDC clock rate. All
communication is initiated and controlled by the host that drives a high-to-low edge to
signal the beginning of each bit time. Commands and data are sent most significant
bit first (MSB first). For a detailed description of the communications protocol, see
Section 9.2.2 "Communication details".
If a host is attempting to communicate with a target MCU that has an unknown BDC
clock rate, a SYNC command may be sent to the target MCU to request a timed sync
response signal from which the host can determine the correct communication speed.
BKGD/PTA4 is a pseudo-open-drain pin and there is an on-chip pullup so no external
pullup resistor is required. Unlike typical open-drain pins, the external RC time constant
on this pin, which is influenced by external capacitance, plays almost no role in signal
rise time. The custom protocol provides for brief, actively driven speedup pulses to force
rapid rise times on this pin without risking harmful drive level conflicts. See Figure 1 for
more detail.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal
pullup on BKGD/PTA4 chooses normal operating mode. When a debug pod is connected
to BKGD/PTA4, it is possible to force the MCU into ACTIVE BACKGROUND mode
after reset. The specific conditions for forcing ACTIVE BACKGROUND depend upon
the HCS08 derivative. See Section 9.1. It is not necessary to reset the target MCU to
communicate with it through the BACKGROUND DEBUG interface.
9.2.2 Communication details
The BDC serial interface requires the external controller to generate a falling edge on the
BKGD/PTA4 pin to indicate the start of each bit time. The external controller provides this
falling edge whether data is transmitted or received.
BKGD/PTA4 is a pseudo-open-drain pin that can be driven either by an external
controller or by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit
(nominal speed). The interface times out if 512 BDC clock cycles occur between falling
edges from the host. Any BDC command that was in progress when this timeout occurs
is aborted without affecting the memory or operating mode of the target MCU system.
The custom serial protocol requires the debug pod to know the target BDC
communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the
user to select the BDC clock source. The BDC clock source can either be the bus or the
alternate BDC clock source.
The BKGD/PTA4 pin can receive a high or low level or transmit a high or low level. The
following diagrams show timing for each of these cases. Interface timing is synchronous
to clocks in the target BDC, but asynchronous to the external host. The internal BDC
clock signal is shown for reference in counting cycles.
Figure 8 shows an external host transmitting a logic 1 or 0 to the BKGD/PTA4 pin of a
target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle
delay from the host-generated falling edge to where the target perceives the beginning
of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the
BKGD/PTA4 pin. Typically, the host actively drives the pseudo-open-drain BKGD/PTA4
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