NXP Semiconductors UM11227 - Tab. 92. LF Receiver Control D Register (LFCTRLD) (Address $0029); Tab. 93. LFCTRLD Register Field Descriptions; 9 LF Receiver Control D Register (LFCTRLD)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Field Description
2:0
AZSC[2:0]
AZSC[2:0] – Log Amp Auto-zero Sequencer Control The 3 bits AZSC[2:0] control the AZ and trim within the
LOGAMP.
x 0 0 = Nominal AZ sequence - recommended setting
x 0 1 = Short amp output release, max delay with Rectifiers
x 1 0 = Short amp output release, max delay with Amp input
x 1 1 = All short, max delay with end of AZ
0 x x = Nominal sensitivity trim - recommended setting
1 x x =Sensitivities shifted by - 4 trim steps
0 0 1 = Result of power on or LFR reset. Existing state remains after all other reset types.
10.15.17.9 LF receiver control D register (LFCTRLD)
Table 92. LF receiver control D register (LFCTRLD) (address $0029)
Bit 7 6 5 4 3 2 1 0
R DEQS
W
AVFOF1 AVFOF0
—
AZDC1 AZDC0 ONMODE CH125K1 CH125K0
Reset U U U U U U U U
POR ($01) 0 0 0 0 0 0 0 1
LFR soft
reset
0 0 U 0 0 0 0 1
Table 93. LFCTRLD register field descriptions
Field Description
7:6
AVFOF[1:0]
AVFOF[1:0] – Auto Zero Release Delay
The two bits AVFOF[1:0] control the delay between falling edge of the SUM d_az_en input and falling edge
of internal AZ control line.
0 0 = No delay; Result of power on or LFR reset. Existing state remains after all other reset types.
0 1 = No delay
1 0 = One-half of 125 kHz clock period delay - recommended setting
1 1 = One and one-half of 125 kHz clock periods delay
5
DEQS
DEQS – DeQing Status Flag
This read-only status bit allows the reading of the effective activation of the DeQing System.
0 = DeQing system not activated; Result of power-on reset. Existing state remains after all other reset types.
1 = DeQing system activated
4:3
AZDC[1:0]
AZDC[1:0] – Auto Zero Triggering Control
In data receive mode, the two bits AZDC[1:0] control the triggering of AZ sequence with respect to both
LFCPTAZ value (ref. LFCTRLB register) and the state of the demodulation input data state.
0 0 = AZ starts after LFCPTAZ numbers of input data edges; Result of power on or LFR reset. Existing state
remains after all other reset types.
0 1 = Z starts randomly adding -1, 0 or 1 to LFCPTAZ value between each AZ.
1 0 = AZ starts after LFCPTAZ numbers of input data edges and when the input data (d_data) state is 0.
1 1 = AZ starts after LFCPTAZ numbers of input data edges and when the input data (d_data) state is 1 -
recommended setting.