NXP Semiconductors UM11227 - Timer Counter High and Low Registers (TPMCNTH;L)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Field Description
6
TOIE
TOIE – Timer Overflow Interrupt Enable
This read/write bit enables TPM1 overflow interrupts. If TOIE is set, an interrupt is generated when TOF
equals 1.
0 = TOF interrupts inhibited (use software polling); Result of Reset
1 = TOF interrupts enabled
5
CPWMS
CPWMS – Center-aligned PWM Select
This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM1 operates in up-
counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS
reconfigures the TPM1 to operate in up-/down-counting mode for CPWM functions.
0 = All TPM channels operate as input capture, output compare, or edge-aligned PWM mode as selected by
the MSnB:MSnA control bits in each channel’s status and control register; Result of Reset
1 = All TPM channels operate in center-aligned PWM mode
4:3
CLKS[B:A]
CLKS[B:A] – Clock Source Select
The 2-bits CLKS[B:A] are used to disable the TPM1 system or select one of three clock sources to drive the
counter prescaler. The internal DX source is synchronized to the bus clock by an on-chip synchronization
circuit.
0 0 = No source selected, TPM disabled; Result of Reset
0 1 = Bus clock selected
1 0 = undefined, TPM enabled but not clocking
1 1 = Internal Dx clock from RF module selected, approx. 500 kHz
[2:0]
PS[2:0]
PS[2:0] – Prescale Divisor Selection
The 3-bits PS[2:0] selects one of eight divisors for the TPM1 clock input. This prescaler is located after any
clock source synchronization or clock source selection, so it affects whatever clock source is selected to
drive the TPM1 system.
0 0 0 = divide by 1; Result of Reset
0 0 1 = divide by 2
0 1 0 = divide by 4
0 1 1 = divide by 8
1 0 0 = divide by 16
1 0 1 = divide by 32
1 1 0 = divide by 64
1 1 1 = divide by 128
10.13.3.2 Timer counter high and low registers (TPMCNTH/L)
Table 47. Timer counter high register (TPMCNTH) (address $0011)
Bit 7 6 5 4 3 2 1 0
R
W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Reset ($00) 0 0 0 0 0 0 0 0
Table 48. Timer counter low register (TPMCNTL) (address $0012)
Bit 7 6 5 4 3 2 1 0
R
W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Reset ($00) 0 0 0 0 0 0 0 0