NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent
other interrupts while in the interrupt service routine. Although it is possible to clear the I
bit with an instruction in the interrupt service routine, this would allow nesting of interrupts
(which is not recommended because it leads to programs that are difficult to debug and
maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index
register pair (H) is not saved on the stack as part of the interrupt sequence. The user
must use a PSHH instruction at the beginning of the service routine to save H and then
use a PULH instruction just before the RTI that ends the interrupt service routine. It is not
necessary to save H if you are certain that the interrupt service routine does not use any
instructions or auto-increment addressing modes that might change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not
masked by the global I bit in the CCR and it is associated with an instruction opcode
within the program so it is not asynchronous to program execution.
8.5.3 WAIT mode operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts
the clocks to the CPU to reduce overall power consumption while the CPU is waiting for
the interrupt or reset event that will wake the CPU from WAIT mode. When an interrupt
or reset event occurs, the CPU clocks resume and the interrupt or reset event are
processed normally.
If a serial BACKGROUND command is issued to the MCU through the BACKGROUND
DEBUG interface while the CPU is in WAIT mode, CPU clocks resume and the CPU
enters ACTIVE BACKGROUND mode where other serial BACKGROUND commands
can be processed. This ensures that a host development system can still gain access to
a target MCU even if it is in WAIT mode.
8.5.4 STOP mode operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during
STOP mode to minimize power consumption. In such systems, external circuitry is
needed to control the time spent in STOP mode and to issue a signal to wake up the
target MCU when it is time to resume processing. Unlike the earlier M68HC05 and
M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of clocks running
in STOP mode. This optionally allows an internal periodic signal to wake the target MCU
from STOP mode.
When a host debug system is connected to the BACKGROUND DEBUG pin (BKGD) and
the ENBDM control bit has been set by a serial command through the BACKGROUND
interface (or because the MCU was reset into ACTIVE BACKGROUND mode), the
oscillator is forced to remain active when the MCU enters STOP mode. In this case, if
a serial BACKGROUND command is issued to the MCU through the BACKGROUND
DEBUG interface while the CPU is in STOP mode, CPU clocks resume and the CPU
enters ACTIVE BACKGROUND mode where other serial BACKGROUND commands
can be processed. This ensures that a host development system can still gain access to
a target MCU even if it is in STOP mode.
Recovery from STOP mode depends on the particular HCS08 and whether the oscillator
was stopped in STOP mode. See Section 10.8 "Modes of operation" for more details.
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