NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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It is a good programming practice to write to the port data register before changing the
direction of a port pin to become an output. This ensures that the pin will not be driven
momentarily with an old data value that happened to be in the port data register.
An internal pullup device can be enabled for each port pin by setting the corresponding
bit in one of the pullup enable registers (PTxPEn). The pullup device is disabled if the
pin is configured as an output by the general purpose I/O control logic or any shared
peripheral function regardless of the state of the corresponding pullup enable register bit.
The pullup device is also disabled if the pin is controlled by an analog function.
10.12.1.1.1 Unused pin configuration
Any general purpose I/O pins which are not used in the application must be properly
configured to avoid a floating input that could cause excessive supply current, I
DD
.
When the device comes out of the reset state the NXP supplied firmware will not
configure any of the general purpose I/O pins.
Recommended configuration methods are:
1. Configure the general purpose I/O pin as an input (PTxDDn = 0) with the pin
connected to the V
DD
source; use a pullup resistor of 10-51 kΩ to assure sufficient
noise immunity.
2. Configure the general purpose I/O pin as an input (PTxDDn = 0) with the internal
pullup activated (PTxPEn = 1) and leave the pin disconnected.
3. Configure the general purpose I/O pin as an output (PTxDDn = 1) and drive the pin
low (PTxDn = 0) and leave the pin disconnected.
In cases where GPIOs are directly connected to AV
DD
, V
DD
, AV
SS
, V
SS
or RV
SS
, user
application should configure the GPIO as an input with the internal pull-up disabled,
in order to prevent software code faults from causing excessive supply current states
should these pins become outputs.
10.12.1.1.2 Pin behavior in STOP modes
Pin behavior following execution of a STOP instruction depends on the STOP mode that
is entered. An explanation of pin behavior for the various STOP modes follows:
• In STOP1 mode, all internal registers including general purpose I/O control and data
registers are powered off. Each of the pins assumes its default reset state (input buffer,
output buffer and internal pullup disabled). Upon exit from STOP1, all pins must be
reconfigured the same as if the MCU had been reset.
• In STOP4 mode, all pin states are maintained because internal logic stays powered up.
Upon recovery, all pin functions are the same as before entering STOP4.
10.12.1.2 Port A data register (PTAD)
Table 24. Port A data register (PTAD) (address $0000)
Bit 7 6 5 4 3 2 1 0
R
W
reserved reserved reserved PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
Reset ($00) 0 0 0 0 0 0 0 0
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