NXP Semiconductors UM11227 - Tab. 109. RFM Control 3 Register (RFCR3) (Address $1833); Tab. 110. RFCR3 Register Field Descriptions; Tab. 111. RFM Control 4 Register (RFCR4) (Address $1834); 4 RFM Control 3 Register (RFCR3)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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10.16.11.4 RFM control 3 register (RFCR3)
Table 109. RFM control 3 register (RFCR3) (address $1833)
Bit 7 6 5 4 3 2 1 0
R
W
DATA IFPD ISPC IFID FNUM3 FNUM2 FNUM1 FNUM0
Reset ($00) 0 0 0 0 0 0 0 0
Table 110. RFCR3 register field descriptions
Field Description
7
DATA
DATA – Data State
The DATA bit determines the output state of the RF power amplifier when the RFM is in the MCU direct
control mode (CODE[1:0] = 11)
0 = RF output state low; Result of Reset
1 = RF output state high.
6
IFPD
IFPD – Interframe Power Down Control
The IFPD control bit selects whether the XCO and associated analog blocks are powered down during
interframe timing caused by the RFM. The IFPD control bit is cleared by the RFMRST signal. The restart of
these functions will start 1 ms before the end of the timing interval if another frame is to be transmitted.
0 = The XCO remains powered up as long as the SEND bit is set; Result of Reset
1 = The XCO is powered down during RFM controlled interframe timing events.
5
ISPC
ISPC – Interframe Random Space Control
When the ISPC bit is set the initial time delay before the first frame will be enabled. This bit is cleared by an
RFM reset.
0 = No initial time interval; Result of Reset
1 = Initial time interval enabled.
4
IFID
IFID – Interframe Interrupt Delay Control
The IFID control bit selects how the RFIF bit will be managed. The IFID control bit is cleared by the
RFMRST signal.
0 = The RFIF bit is set and the MCU interrupted if the RFIEN bit is set, after the last frame transmitted;
Result of Reset
1 = The RFIF bit is set and the MCU interrupted if the RFIEN bit is set, only after the last frame plus an
additional interframe message is transmitted.
3:0
FNUM[3:0]
FNUM[3:0] – Number of Frames
The 4 bits FNUM[3:0] bits set the number of frames transmitted in each RF datagram. The frames will be
randomly spaced apart as described in bits 6, 5 and 4. These bits are cleared by an RFM reset. The number
of frames transmitted is the binary number plus one.
0 0 0 0 = Result of Reset
10.16.11.5 RFM control 4 register (RFCR4)
Table 111. RFM control 4 register (RFCR4) (address $1834)
Bit 7 6 5 4 3 2 1 0
R
W
RFBT7 RFBT6 RFBT5 RFBT4 RFBT3 RFBT2 RFBT1 RFBT0
Reset ($80) 1 0 0 0 0 0 0 0