NXP Semiconductors UM11227 - Timer Modulo High and Low Registers (TPMMODH;L); Timer Channel 0;1 Status and Control Registers (Tpmcysc)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Table 49. TPMCNTH/L register field descriptions
Field Description
15:0 The two read-only TPMCNT[15:0] counter registers contain the high and low bytes of the value in the TPM1
counter. Reading either byte (TPM1CNTH or TPM1CNTL) latches the contents of both bytes into a buffer
where they remain latched until the other byte is read. This allows coherent 16-bit reads in either order.
The coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPM1CNTH
or TPM1CNTL, or any write to the timer status/control register (TPM1SC). Reset clears the TPM1 counter
registers.
10.13.3.3 Timer modulo high and low registers (TPMMODH/L)
Table 50. Timer modulo high register (TPMMODH) (address $0013)
Bit 7 6 5 4 3 2 1 0
R
W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Reset ($00) 0 0 0 0 0 0 0 0
Table 51. Timer modulo low register (TPMMODL) (address $0014)
Bit 7 6 5 4 3 2 1 0
R
W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Reset ($00) 0 0 0 0 0 0 0 0
Table 52. TPMMODH/L register field descriptions
Field Description
15:0 The read/write TPMMOD[15:0] modulo registers contain the modulo value for the TPM1 counter. After the
TPM1 counter reaches the modulo value, the TPM1 counter resumes counting from 0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPM1MODH or TPM1MODL inhibits TOF and overflow interrupts until the other byte is written. Reset
results in a free-running timer counter (i.e. modulo disabled).
$0000 = Result of Reset
10.13.3.4 Timer channel 0/1 status and control registers (TPMCySC)
Where y = Channel 0 or Channel 1.
Table 53. Timer channel 0 status and control register (TPMC0SC) (address $0015)
Bit 7 6 5 4 3 2 1 0
R CH0F 0 0
W —
CH0IE MS0B MS0A ELS0B ELS0A
— —
Reset ($00) 0 0 0 0 0 0 0 0