NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Table 54. Timer channel 1 status and control register (TPMC1SC) (address $0018)
Bit 7 6 5 4 3 2 1 0
R CH1F 0 0
W —
CH1IE MS1 MS1A ELS1B ELS1A
— —
Reset ($00) 0 0 0 0 0 0 0 0
Table 55. TPMCySC register field descriptions
Field Description
7
CH0/1F
CHyF – Channel 0/1 Flag
When channel n is configured for input capture, this read-only CHyF bit is set when an active edge occurs
on the channel 0/1 pin. When channel 0/1 is an output compare or edge-aligned PWM channel, CHyF is set
when the value in the TPM1 counter registers matches the value in the TPM1 channel 0/1 value registers.
This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the
channel value register, which corresponds to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHyF is set and interrupts are enabled (CHyIE = 1). Clear
CHyF by reading TPM1CySC while CHyF is set and then writing a 0 to CHyF. If another interrupt request
occurs before the clearing sequence is complete, the sequence is reset so CHyF would remain set after the
clear sequence was completed for the earlier CHyF. This is done so a CHyF interrupt request cannot be lost
by clearing a previous CHyF. Writing a 1 to CHyF has no effect.
0 = No input capture or output compare event occurred on channel 0; Result of power-on reset.
1 = Input capture or output compare event occurred on channel 0; Result of other reset types.
6
CH0/1IE
CHyiE – Channel 0/1 Interrupt Enable
This read/write bit enables interrupts from channel 0/1.
0 = Channel 0/1 interrupt requests disabled (use software polling); Result of Reset
1 = Channel 0/1 interrupt requests enabled
5:4
MS0.1[B;a]
MSy[B:A] – Channel 0/1 Mode Select
When CPWMS = 0, MSyB = 1 configures TPM1 channel 0/1 for edge-aligned PWM mode. When CPWMS =
0 and MSyB = 0, MSyA configures TPM1 channel 0/1 for input capture mode or output compare mode.
3:2
ELS0/1[B:A]
ELSy[B:A] – Channel 0/1 Edge/Level Select
Depending on the operating mode for the timer channel as set by CPWMS:MSyB:MSyA and shown below,
these bits select the polarity of the input edge that triggers an input capture event, select the level that
will be driven in response to an output compare match, or select the polarity of the PWM output. Setting
ELSyB:ELSyA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer
channel functions. This function is typically used to temporarily disable an input capture channel or to
make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a
software timer that does not require the use of a pin.
Table 56. Timer channel operating mode settings
CPWMS MSy[B:A] ELSy[B:A] Mode
x x 0 0 Pin not used for TPM1 channel; use as an external clock for the TPM1 or revert to
general-purpose I/O; Result of Reset
0 0 0 0 1 Input capture rising edge
0 0 0 1 0 Input capture falling edge
0 0 0 1 1 Input capture rising or falling edges
0 0 1 0 0 Output compare software monitor
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