NXP Semiconductors UM11227 - Duty Cycle for Data Mode

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
88 / 205
half of the bit time as shown in Figure 21. Another way to say this from the point of view
of the data slicer output is that a logic zero bit has a falling edge at the middle of the bit
time and a logic one bit has a rising edge at the middle of the bit time. The data slicer
threshold is dynamically adjusted to the midpoint between the carrier-present and no-
carrier levels at the summing node for the rectified output of the LF input amplifier.
T
logic 1
T
logic 0
0.5 T 0.5 T
aaa-028021
LF input
(shaded area
is LF carrier)
Data bit
(data slicer
output)
Data slicer threshold
T = 1 bit time at the data rate (ex. 256 s at data rate of 3.906 kbps)
Figure 21. Manchester encoded datagram for LFPOL = 0
When the LFPOL bit is set, a logic one bit is defined as LF carrier present for the first half
of the bit time; and a logic zero bit is defined as no LF carrier present for the first half of
the bit time as shown in Figure 21.
T
logic 0
T
logic 1
0.5 T 0.5 T
aaa-028022
LF input
(shaded area
is LF carrier)
Data bit
(data slicer
output)
Data slicer threshold
T = 1 bit time at the data rate (ex. 256 s at data rate of 3.906 kbps)
Figure 22. Manchester encoded datagram for LFPOL = 1
10.15.11 Duty cycle for data mode
The definition of the duty cycle for the Manchester encoded data depends on the relative
rise and fall times of the incoming LF carrier as shown in Figure 23.
60
60
40
40
1 0
aaa-028023
Figure 23. Definition of duty cycle of 40 %
Regarding the SYNC pattern which is non-Manchester coded, the duty cycle is applied
on all falling edges with the same proportion as a 1T Manchester symbol, as shown in
Figure 24.