NXP Semiconductors UM11227 - Tab. 152. SMI Settling Time Register (SMIST) (Address $0043); Tab. 153. SMIST Register Field Descriptions; Tab. 154. SP[3:0]; SMI Settling Time Register (SMIST)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
149 / 205
Field Description
1:0
FILT[1:0]
FILT[1:0] – Low-pass Filter selection
When the FILEN bit is 1, the two bits FILT[1:0] select the cut-off frequency of the low-pass filter. When the
FILEN bit is 0, writing to the FILT[1:0] bits has no effect and default to the low-pass filter being bypassed
0 0 = 250 Hz; Result of Reset. This setting induces an offset until the input signal has completely settled,
and therefore consumes additional energy; NXP recommends using the 500 Hz, 1000 Hz, or 2000 Hz
settings where absolute accuracy and lowest energy consumption are needed.
0 1 = 500 Hz
1 0 = 1000 Hz
1 1 = 2000 Hz
10.19.2.4 SMI settling time register (SMIST)
Table 152. SMI settling time register (SMIST) (address $0043)
Bit 7 6 5 4 3 2 1 0
R
W
SP3 SP2 SP1 SP0 ISD3 ISD2 ISD1 ISD0
Reset ($00) 0 0 0 0 0 0 0 0
Table 153. SMIST register field descriptions
Field Description
7:4
SP[3:0]
SP[3:0] - Subsequent sample delay
The SMI settling time register holds the subsequent sample delay (SP) in the four most-significant bits.
The function maps a binary pattern programmed by the application to a defined count of MFO cycles
approximating the SP time selections.
The four most-significant bits are used to program the subsequent sample delay (SP) periods. The SP[3:0]
control bits result in the approximate subsequent sample delay periods as follows:
0 0 0 0 = Result of Reset. See Table 154.
3:0
ISD[3:0]
ISD[3:0] - Initial sample delay
The SMI settling time register holds the initial sample delay (ISD) period in the four least-significant bits.
The function maps a binary pattern programmed by the application to a defined count of MFO cycles
approximating the IDS time selections.
The four least-significant bits are used to program the initial sample delay (ISD) period. The ISD[3:0] control
bits result in the approximate initial sample delay as follows:
0 0 0 0 = Result of Reset. See Table 155.
Table 154. SP[3:0]
SP[3:0] Number of MFO Clock Cycles ~T
SP
Nom. Sample Per. (us)
0000 8 64
0001 10 80
0010 13 104
0011 16 128
0100 20 160
0101 25 200