NXP Semiconductors UM11227 - Tab. 189. FOPT and NVOPT Register Field Descriptions. 178 Tab. 190. FMC Configuration Registers (FCNFG) (Address $1823); Tab. 191. FCNFG Register Field Descriptions; Tab. 192. Flash Protection Register (FPROT) (Address $1824); Tab. 193. Flash Protection Register (NVPROT) (Address $FFBD)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
179 / 205
Field Description
1:0
SEC[1:0]
SEC[1:0] – Security State Code
The two bits SEC[1:0] select the security state of the MCU as shown below. When the MCU is secure,
the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source
including the BACKGROUND DEBUG interface. SEC[1:0] changes to 1 0 after successful backdoor key
entry or a successful blank check of FLASH. When secured, the SPI may access only the address ranges
$0000 to $008F and $1800 to $188F. Other access attempts will result in an error status.
0 0 = secured
0 1 = secured
1 0 = unsecured (default from NXP factory)
1 1 = secured (default after erase of the block $FE00 - $FFFF)
10.24.9.3 FMC configuration registers (FCNFG)
Table 190. FMC configuration registers (FCNFG) (address $1823)
Bit 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
W — —
KEYACC
— — — — —
Reset ($00) 0 0 0 0 0 0 0 0
Table 191. FCNFG register field descriptions
Field Description
5
KEYACC
KEYACC - This bit enables writing of the backdoor comparison key.
0 Writes to $FFB0–$FFB7 are interpreted as the start of a FLASH programming or erase command; Result
of Reset
1 Writes to NVBACKKEY ($FFB0–$FFB7) are interpreted as comparison key writes.
10.24.9.4 Flash protection registers (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT is copied from FLASH into
FPROT. Bits 0, 1, and 2 are not used and each always reads as 0. This register can be
read at any time, but user program writes have no meaning or effect. BACKGROUND
DEBUG commands can write to FPROT.
Table 192. Flash protection register (FPROT) (address $1824)
Bit 7 6 5 4 3 2 1 0
R
W
FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS
All resets from $FFBD from $FFBD from $FFBD from $FFBD from $FFBD from $FFBD from $FFBD from $FFBD
Table 193. Flash protection register (NVPROT) (address $FFBD)
Bit 7 6 5 4 3 2 1 0
R
W
FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS
All resets from BDM from BDM from BDM from BDM from BDM from BDM from BDM from BDM