NXP Semiconductors UM11227 - Tab. 184. FMC Clock Divider Register (FCDIV) (Address $1820); Tab. 185. FCDIV Register Field Descriptions; Tab. 186. FMC Clock Divider Register Settings; FMC Register Descriptions

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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10.24.9 FMC register descriptions
10.24.9.1 FMC clock divider register (FCDIV)
Table 184. FMC clock divider register (FCDIV) (address $1820)
Bit 7 6 5 4 3 2 1 0
R DIVLD
W —
PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
Reset ($00) 0 0 0 0 0 0 0 0
Table 185. FCDIV register field descriptions
Field Description
7
DIVLD
DIVLD – Divisor Loaded Status Flag
When set, this read-only in user mode status flag indicates that the FCDIV register has been written since
reset. Reset clears this bit and the first write to this register causes this bit to become set regardless of the
data written. This bit can be written in flash test mode while the FDONE bit remains = 1.
0 = FCDIV has not been written since reset; erase and program operations disabled for FLASH; Result of
Reset
1 = FCDIV has been written since reset; erase and program operations enabled for FLASH
6
PRDIV8
PRDIV8 – Write-once in user mode, Prescale (Divide) FLASH Clock by 8.
This bit can be written or read in flash test mode while the FDONE bit remains = 1.
0 = Clock input to the FLASH clock divider is the bus rate clock; Result of Reset
1 = Clock input to the FLASH clock divider is the bus rate clock divided by 8
5
DIV[5:0]
DIV[5:0] – Divisor for FLASH Clock Divider
The FLASH clock divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by
the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the internal FLASH clock must
fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/Erase timing pulses
are one cycle of this internal FLASH clock which corresponds to a range of 5 µs to 6.7 µs. The automated
programming logic uses an integer number of these pulses to complete an erase or program operation.
• if PRDIV8 = 0 — f
FCLK
= fBUS / ( DIV[5:0] + 1 )
• if PRDIV8 = 1 — f
FCLK
= fBUS / ( 8 / ( DIV[5:0] + 1 ) )
0 0 0 0 0 0 = Result of Reset.
These bits can be written or read in flash test mode while the FDONE bit remains = 1.
Table 186. FMC clock divider register settings
f
Bus
(MHz)
PRDIV8
(Binary)
DIV5:0
(Decimal)
f
FLCK
(kHz)
Program/Erase Timing Pulse
(5 µs Min, 6.7 µs Max)
(µs)
20 1 12 192.3 5.2
10 0 49 200 5
8 0 39 200 5
4 0 19 200 5
2 0 9 200 5
1 0 4 200 5