NXP Semiconductors UM11227 - Periodic Wake-Up Reset Register (PWUCS1); Periodic Wake-Up Counter Register (PWUS)

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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10.14.1.4 Periodic wake-up reset register (PWUCS1)
Table 68. Periodic wake-up reset register (PWUCS1) (address $001E)
Bit 7 6 5 4 3 2 1 0
R
W
PRST7 PRST6 PRST5 PRST4 PRST3 PRT2 PRST1 PRST0
Reset ($FF) 1 1 1 1 1 1 1 1
Table 69. PWUCS1 register field descriptions
Field Description
[7:0]
PRST
The PRST[7:0] bits select the number of wake-up interrupts until the next periodic reset is generated.
Periodic reset time PRT = Wake-up interrupt time RCLK x PRST[7:0]
The PRST[7:0] gives a range of periodic reset times from 1 to 255 x wake-up interrupts. Depending on the
value of the bits for the WDIV[7:0] and WUT[7:0] this time interval can nominally be from 0.504 s to 4967.91
minutes with steps from 0.504 s to 1168.92 s.
Whenever the PRST[7:0] bits are changed the timeout period is restarted. Writing the same data to the
PRST[7:0] bits has no effect. Writing zeros to all of the PRST[7:0] bits forces the periodic reset to be
disabled if at least one of the WUT[7:0] bits is set to a one. This assures that there will be at least a wake-up
interrupt. However, writing all zeros to the PRST[7:0] bits is inhibited if all of the WUT[7:0] bits are already
cleared to zero. This prevents disabling both the periodic wake-up and the periodic reset at the same time.
The PRST[7:0] bits are preset to a value of $FF (decimal 255) by any resets.
$FF = Result of power on or periodic wake-up unit reset.
10.14.1.5 Periodic wake-up counter register (PWUS)
Table 70. Periodic wake-up counter register (PWUS) (address $001F)
Bit 7 6 5 4 3 2 1 0
R CSTAT7 CSTAT6 CSTAT5 CSTAT4 CSTAT3 CSTAT2 CSTAT1 CSTAT0
W — — — — — — — —
Reset ($00) 1 1 1 1 1 1 1 1
Table 71. PWUS register field descriptions
Field Description
[7:0]
CSTAT
The CSTAT[7:0] read-only bits show the status of the counter selected by the PSEL bit. The effect of
any reset on these bits depends on how the reset affects the selected counter. Reading these counters
immediately after a WUF or PRF generated flag will return zero contents.
$00 = Result of power on or periodic wake-up unit reset.
Note: Due to a coincident alignment of the LFO clock source for the PWU and the PWUS register, an
inadvertent read of the PWUS may result in corruption of the PWUDIV, PWUCS0, and PWUCS1 registers.
Users are advised to write the PWUDIV, PWUCS0, and PWUCS1 registers just prior to entering a Stop
mode, and avoid reading the PWUS register at that time. If a corruption might be detected during a Run
mode cycle, users should re-write the desired settings for the PWUDIC, PWUCS0, and WPUCS1 registers
prior to entering a Stop mode.