NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Field Description
5
IRQEDG
IRQEDG – The IRQEDG bit selects the edge/low level or rising edge/high level function of the PTA0 pin.
0 = Falling edge/low level, available in all modes; Result of Reset
1 = Rising edge/high level, only available while in Run mode.
4
IRQPE
IRQPE – The IRQPE bit enables the external PTA0 pin to function as the IRQ source.
0 = PTA0 not selected as the IRQ source; Result of Reset
1 = PTA0 selected as the IRQ source.
3
IRQF
IRQF – IRQ pending Flag
The read-only IRQF bit indicates when a wake-up interrupt has been generated by the external IRQ. This bit
is cleared by writing a one to the IRQACK bit. Writing a zero to this bit has no effect.
0 = external interrupt not generated or was previously acknowledged; Result of power-on reset. Existing
state will remain after all other types of reset.
1 = external interrupt generated.
2
IRQACK
IRQACK – IRQ Acknowledge
The write-only IRQACK bit clears the IRQF bit if written with a one. Writing a zero to the IRQACK bit has no
effect on the IRQF bit. Reading the IRQACK bit returns a zero. Reset has no effect on this bit.
0 = Read result; Write no effect; Result of Reset
1 = Write 1 to clear IRQF for IRQ interrupt acknowledge
1
IRQIE
IRQIE – IRQ Interrupt Enable
The IRQIE bit enables or disables the external IRQ interrupt function
0 = IRQ interrupt disabled; Result of Reset
1 = IRQ interrupt enabled
0
IRQMOD
IRQMOD – Keyboard Detection Mode
IRQMOD (along with the IRQEDG bits) controls the detection mode of the keyboard interrupt pins.
0 = IRQ detects on falling or rising edges only; Result of Reset
1 = IRQ detects both edges and levels.
10.13 Timer pulse-width module
The timer pulse-width module (TPM1) is a two channel timer system that supports
traditional input capture, output compare, or edge-aligned PWM on each channel. All
the features and functions of the TPM1 are as described in the MC9S08RC16 product
specification. The user has the option to connect the two timer channels to the PTB[1:0]
pins for interface to external circuits.
The TPM1 has the following features:
• May be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
• Clock sources independently selectable
• Selectable clock sources (device dependent): bus clock, fixed system clock
• Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running or up/down (CPWM) count operation
• 16-bit modulus register to control counter range
• Timer system enable
• One interrupt per channel plus a terminal count interrupt
• Channel features:
– Each channel may be input capture, output compare, or buffered edge-aligned PWM
– Rising-edge, falling-edge, or any-edge input capture trigger
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