NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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stacked on entry to the ISR. In rare cases, the I bit may be cleared inside an ISR
(after clearing the status flag that generated the interrupt) so that other interrupts can
be serviced without waiting for the first service routine to finish. This practice is not
recommended for anyone other than the most experienced programmers because it can
lead to subtle program errors that are difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which
restores the CCR, A, X, and PC registers to their pre interrupt values by reading the
previously saved information off the stack.
When two or more interrupts are pending when the I bit is cleared, the highest priority
source is serviced first.
For compatibility with the M68HC08, the H register is not automatically saved and
restored. It is good programming practice to push H onto the stack at the start of the
interrupt service routine (ISR) and restore it just before the RTI that is used to return from
the ISR.
10.2.1 Interrupt stack frame
Figure 11 shows the contents and organization of a stack frame. Before the interrupt,
the stack pointer (SP) points at the next available byte location on the stack. The current
values of CPU registers are stored on the stack starting with the low-order byte of the
program counter (PCL) and ending with the CCR. After stacking, the SP points at the
next available location on the stack which is the address that is one less than the address
where the CCR was saved. The PC value that is stacked is the address of the instruction
in the main program that would have executed next if the interrupt had not occurred.
When an RTI instruction is executed, these values are recovered from the stack in
reverse order. As part of the RTI sequence, the CPU fills the instruction pipeline by
reading three bytes of program information, starting from the PC address just recovered
from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning
from the ISR. Typically, the flag should be cleared at the beginning of the ISR so that
if another interrupt is generated by this same source, it will be registered so it can be
serviced after completion of the current ISR.
aaa-028000
Condition code register (CCR)
Accumulator
Index register* (low byte x)
Program counter high
Program counter low
Unstacking
order
Stacking
order
SP after
interrupt stacking
SP before
the interrupt
Towards HIGHER addresses
Towards LOWER addresses
7 0
1
2
3
4
5
5
4
3
2
1
* High byte (H) of index register is not automatically stacked.
Figure 11. Interrupt stack frame
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