NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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pin during host-to-target transmissions to speed up rising edges. Because the target
does not drive the BKGD/PTA4 pin during the host-to-target transmission period, there is
no need to treat the line as an open-drain signal during this period.
Earliest start of next bit
Target senses bit level
aaa-028043
10 cycles
Synchronization
uncertinity
BDC clock
(target MCU)
Host
transmit 1
Host
transmit 0
Perceived start
of bit time
Figure 8. BDC host-to-target serial bit timing
Figure 9 shows the host receiving a logic 1 from the target HCS08 MCU. Because the
host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-
generated falling edge on BKGD/PTA4 to the perceived start of the bit time in the target
MCU. The host holds the BKGD/PTA4 pin low long enough for the target to recognize it
(at least two target BDC cycles). The host must release the low drive before the target
MCU drives a brief active-high speedup pulse seven cycles after the perceived start of
the bit time. The host should sample the bit level about 10 cycles after it started the bit
time.
Earliest start of next bit
aaa-028044
Host samples BKGD PTA4 pin
10 cycles
BDC clock
(target MCU)
Host drive to
BKGD/PTA4 pin
BKGD/PTA4 pin
Target MCU
speedup pulse
Perceived start
of bit time
10 cycles
High-impedance High-impedance
High-impedance
R-C rise
Figure 9. BDC target-to-host serial bit timing (Logic 1)
Figure 10 shows the host receiving a logic 0 from the target HCS08 MCU. Because the
host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-
generated falling edge on BKGD/PTA4 to the start of the bit time as perceived by the
target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the
target wants the host to receive a logic 0, it drives the BKGD/PTA4 pin low for 13 BDC
clock cycles, then briefly drives it high to speed up the rising edge. The host samples the
bit level about 10 cycles after starting the bit time.
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