NXP Semiconductors UM11227

To Next Page

To Previous Page

NXP Semiconductors

UM11227

NTM88 family of tire pressure monitor sensors

User manual Rev. 6 — 24 April 2020

163 / 205

aaa-031073

HV CONTROL

LOGIC

Bandgap Out

wakeup1

supply

wakeup2

Reset3p3b

SIM handshake

RTI

wakeup

VOLTAGE

REGULATOR

dda

dda_sw

dd_sw

FRC

RTI

LVD/POR

CIRCUIT

HV DETECT

CIRCUIT

LV CONTROL

LOGIC

REGISTERS

MCU Internal Address, Data, Interrupt, and Control Bus

freeze1

freeze2

RTI Clock

RTI Out

ExtClk

Figure 52. Power management controller module block diagram

Main Page

Introduction1
Purpose1
Audience1
General Description1
Features and Benefits1
Configuration Options2
Electronic Encoding - "Codef2
Electronic Encoding - "Codeh3
Device Identification3
Definition of Signal Ranges4
Memory Resource Usage5
Marking5
Exterior Markings5
Block Diagram6
Pinning Information7
Pinout7
Pin Description7
Orientation10
Central Processing Unit10
Introduction10
Features10
Programmer's Model and CPU Registers11
Accumulator (A)11
Index Register (H:X)12
Stack Pointer (SP)12
Program Counter (PC)12
Condition Code Register (CCR)13
Addressing Modes14
Inherent Addressing Mode (INH)14
Relative Addressing Mode (REL)14
Immediate Addressing Mode (IMM)14
Direct Addressing Mode (DIR)15
Extended Addressing Mode (EXT)15
Indexed Addressing Mode15
Indexed, no Offset (IX)15
Indexed, no Offset with Post Increment (IX+)15
Indexed, 8-Bit Offset (IX1)15
Indexed, 8-Bit Offset with Post Increment (IX1+)15
Indexed, 16-Bit Offset (IX2)15
SP-Relative, 8-Bit Offset (SP1)16
SP-Relative, 16-Bit Offset (SP2)16
Special Operations16
Reset Sequence16
Interrupt Sequence16
WAIT Mode Operation17
STOP Mode Operation17
BGND Instruction18
HCS08 Instruction Set Summary18
Instruction Set Summary Nomenclature18
Operators18
CPU Registers18
Memory and Addressing18
Condition Code Register (CCR) Bits19
CCR Activity Notation19
Machine Coding Notation19
Source Form19
Address Modes20
Development Support31
Introduction31
Features31
Background Debug Controller (BDC)32
BKGD/PTA4 Pin Description32
Communication Details33
BDC Commands35
Coding Structure Nomenclature35
BDC Hardware Breakpoint37
Register Definition38
BDC Registers and Control Bits38
BDC Status and Control Register (BDCSCR)38
BDC Breakpoint Match Register (BDCBKPT)39
System Background Debug Force Reset Register (SBDFR)40
Functional Description40
Register Information40
Register Map40
Register Description Format47
Interrupts48
Interrupt Stack Frame49
Vector Summary50
Interrupt Service Routines50
Low-Voltage Detect (LVD) System51
Power-On Reset Operation51
LVD Reset Operation51
LVD Interrupt Operation52
Low-Voltage Warning (LVW)52
System Clock Control52
Keyboard Interrupts52
Real-Time Interrupt52
Modes of Operation53
Features53
RUN Mode53
WAIT Mode53
ACTIVE BACKGROUND Mode53
STOP Modes54
STOP1 Mode54
STOP4 LVD Enabled in STOP Mode54
Active BDM Enabled in STOP Mode56
MCU On-Chip Peripheral Modules in STOP Modes56
RFM Module in STOP Modes57
P-Cell in STOP Modes58
Optional G-Cell in STOP Modes58
Memory58
Memory Map - Parts Delivered Without Firmware in Flash58
Clock Distribution59
Reset, Interrupts and System Configuration60
Features60
MCU Reset61
Computer Operating Properly (COP) Watchdog61
General Purpose I/O Port Pins62
GPIO Register Descriptions62
General Purpose I/O64
Port a Data Register (PTAD)65
Port a Pin Pull Enable Register (PTAPE)66
Port a Data Direction Register (PTADD)66
Port B Data Register (PTBD)67
Port B Pin Pull Enable Register (PTBE)67
Port B Data Direction Register (PTBDD)67
External Wake-Up Functions68
KBI Status and Control Register (KBISC)68
Keyboard Interrupt Pin Enable Register (KBIPE)69
Keyboard Interrupt Edge Select Register (KBIES)69
Ext. Interrupt Status and Control Register (IRQSC)70
Timer Pulse-Width Module71
TPM1 Configuration Information72
Block Diagram72
External Signal Description73
TPM Register Descriptions73
Timer Status and Control Register (TPMSC)73
Timer Counter High and Low Registers (TPMCNTH/L)74
Timer Modulo High and Low Registers (TPMMODH/L)75
Timer Channel 0/1 Status and Control Registers (Tpmcysc)75
Timer Channel 0/1 Value Registers (Tpmcyvh/L)77
Periodic Wake-Up Timer Module78
PWU Timer Register Descriptions79
Periodic Wake-Up Status and Control Register (PWUSR)79
Periodic Wake-Up Divider Register (PWUDIV)80
Periodic Wake-Up Interrupt Register (PWUCS0)80
Periodic Wake-Up Reset Register (PWUCS1)81
Periodic Wake-Up Counter Register (PWUS)81
Low Frequency (LF) Receiver Module82
Features83
Modes of Operation83
Power Management83
Input Amplifier84
LFR Data Mode States84
Carrier Detect84
Auto-Zero Sequence87
Data Recovery87
Data Clock Recovery and Synchronization87
Manchester Decode87
Duty Cycle for Data Mode88
Input Signal Envelope89
Telegram Verification89
Error Detection and Handling91
Continuous on Mode91
Initialization Information91
LF Receiver Module Register Descriptions92
1LF Control 1 Register (LFCTL1)92
2LF Control 2 Register (LFCTL2)93
3LF Control 3 Register (LFCTL3)94
4LF Control 4 Register (LFCTL4)96
Tab. 83. LF Receiver Status Register (LFS) (Address $0024)97
5LF Receiver Status Register (LFS)97
Tab. 84. LFS Register Field Descriptions98
Tab. 85. LF Received Data Register (LFDATA) (Address $0025)99
Tab. 86. LFDATA Register Field Descriptions99
Tab. 87. LF Receiver ID Register (LFID) (Address $0026)99
6LF Received Data Register (LFDATA)99
7LF Receiver ID Registers (LFID)99
Tab. 88. LF Receiver ID Register (LFID) (Address $0027)100
Tab. 89. LFID Register Field Descriptions100
Tab. 90. LF Receiver Control E Register (LFCTRLE) (Address $0028)100
Tab. 91. LFCTRLE Register Field Descriptions100
8LF Receiver Control E Register (LFCTRLE)100
Tab. 92. LF Receiver Control D Register (LFCTRLD) (Address $0029)101
Tab. 93. LFCTRLD Register Field Descriptions101
9LF Receiver Control D Register (LFCTRLD)101
Tab. 94. LF Receiver Control C Register (LFCTRLC) (Address $002A)102
Tab. 95. LFCTRLC Register Field Descriptions102
LF Receiver Control C Register (LFCTRLC)102
Tab. 96. LF Receiver Control B Register (LFCTRLB) (Address $002B)103
Tab. 97. LFCTRLB Register Field Descriptions103
LF Receiver Control B Register (LFCTRLB)103
Tab. 98. LF Receiver Control a Register (LFCTRLA) (Address $002C)104
Tab. 99. LFCTRLA Register Field Descriptions104
LF Receiver Control a Register (LFCTRLA)104
Radio Frequency (RF) Transmitter Module104
RF Data Modes105
RF Data Buffer Mode105
MCU Direct Mode106
RF Output Buffer Data Frame107
Data Buffer Length107
End of Message (EOM)107
RF Transmission Randomization107
Initial Time Interval108
Interframe Time Intervals108
Base Time Interval109
Pseudo-Random Time Interval109
Tab. 100. Randomization Interval Times110
Frame Number Time110
Tab. 101. Frame Number Interval Times111
RFM in STOP1 Mode111
Data Encoding111
Manchester Encoding111
Bi-Phase Encoding112
NRZ Encoding112
RF Output Stage114
Modulation Method114
Carrier Frequency114
RF Power Output114
Transmission Error115
Supply Voltage Check During RF Transmission115
RF Reset (RFMRST)115
RF Interrupt115
Datagram Transmission Times115
Pre-Charge Function116
VCO Calibration Machine116
Tab. 102. RFM Control 0 Register (RFCR0) (Address $1830)117
RFM Register Descriptions117
1RFM Control 0 Register (RFCR0)117
Tab. 103. RFCR0 Register Field Descriptions118
Tab. 104. Data Rate Option Examples118
Tab. 105. RFM Control 1 Register (RFCR1) (Address $1831)118
Tab. 106. RFCR1 Register Field Descriptions118
2RFM Control 1 Register (RFCR1)118
Tab. 107. RFM Control 2 Register (RFCR2) (Address $1832)119
Tab. 108. RFCR2 Register Field Descriptions119
3RFM Control 2 Register (RFCR2)119
Tab. 109. RFM Control 3 Register (RFCR3) (Address $1833)120
Tab. 110. RFCR3 Register Field Descriptions120
Tab. 111. RFM Control 4 Register (RFCR4) (Address $1834)120
4RFM Control 3 Register (RFCR3)120
5RFM Control 4 Register (RFCR4)120
Tab. 112. RFCR4 Register Field Descriptions121
Tab. 113. RFM Control 5 Register (RFCR5) (Address $1835)121
Tab. 114. RFCR5 Register Field Descriptions121
Tab. 115. RFM Control 6 Register (RFCR6) (Address $1836)121
Tab. 116. RFCR6 Register Field Descriptions121
6RFM Control 5 Register (RFCR5)121
7RFM Control 6 Register (RFCR6)121
Tab. 117. RFM Control 7 Register (RFCR7) (Address $1837)122
Tab. 118. RFCR7 Register Field Descriptions122
8RFM Control 7 Register (RFCR7)122
Tab. 119. RFM Phase Lock Loop Control Register 0 (PLLCR0) (Address $1838)123
Tab. 120. RFM Phase Lock Loop Control Register 1 (PLCCR1) (Address $1839)123
Tab. 121. RFM Phase Lock Loop Control Register 2 (PLCCR2) (Address $183A)123
Tab. 122. RFM Phase Lock Loop Control Register 3 (PLCCR3) (Address $183B)123
Pllcr3)123
Tab. 123. PLLCR0 / PLLCR1 / PLLCR2 / PLLCR3 Register Field Descriptions124
Tab. 124. RFM Transmit Data 0 through 31 Registers (RFTX0 : RFTX31) (Addresses $183C : $185B)125
RFM Transmit Data 0 through 31 Registers (RFTX0 : RFTX31)125
Tab. 125. RFTX0 : RFTX31 Register Field Descriptions129
Tab. 126. RFM EOM, PLL and PA Control Register (EPR) (Address $1860)129
Tab. 127. EPR Register Field Descriptions129
RFM EOM, PLL and PA Control Register (EPR)129
Tab. 128. RFM Pre-Charge Control Register (RFPRECHARGE) (Address $1861)130
Tab. 129. RFPRECHARGE Register Field Descriptions130
RFM Pre-Charge Control Register (RFPRECHARGE)130
Analog-To-Digital Converter (ADC) Module130
Tab. 130. ADC Status and Control 1 Register (ADSC1) (Address $0030)132
Tab. 131. ADSC1 Register Field Descriptions132
Tab. 132. ADCH Valid Channel Values132
ADC Register Descriptions132
ADC Status and Control 1 Register (ADSC1)132
Tab. 133. ADC Status and Control 2 Register (ADSC2) (Address $0031)133
Tab. 134. ADSC2 Register Field Descriptions133
ADC Status and Control 2 Register (ADSC2)133
Tab. 135. ADC Result High Register (ADRH) (Address $0032)134
Tab. 136. ADC Result Low Register (ADRL) (Address $0033)134
ADC Result High and Low Registers (ADRH/L)134
Tab. 137. ADRH/L Register Field Descriptions135
Tab. 138. ADCV Compare Value High Register (ADCVH) (Address $0034)135
Tab. 139. ADCV Compare Value Low Register (ADCVL) (Address $0035)135
Tab. 140. ADCVH/L Register Field Descriptions135
Tab. 141. ADC Configuration Register (Address $0036)135
ADC Compare Value High and Low Registers (ADCVH/L)135
ADC Configuration Register135
Tab. 142. ADC Register Field Descriptions136
Tab. 143. Port Pin Control Register (Address $0037)136
Tab. 144. Port Pint Control Register Field Descriptions136
Port Pin Control Register136
Serial Peripheral Interface (SPI) Module137
SPI Protocol Definition138
SPI Signal Timing Definition139
Sensor Measurement Interface (SMI) Module140
SMI Signal Measurement Modes141
Tab. 145. Signal Measurement Sub-Modes142
SMI Automatic Signal Measurement Mode142
SMI Direct Sensor Signal Measurement Mode143
SMI Low Power Direct Sensor Signal Measurement Mode144
Tab. 146. SMI Status and Control Register (SMICS) (Address $0040)146
Tab. 147. SMICS Register Field Descriptions146
SMI Register Descriptions146
SMI Status and Control Register (SMICS)146
Tab. 148. SMI Control Register (SMIC) (Address $0041) . 147 Tab. 149. SMIC Register Field Descriptions147
SMI Control Register (SMIC)147
Tab. 150. SMI Configuration Register (SMICFG) (Address $0042)148
Tab. 151. SMICFG Register Field Descriptions148
SMI Configuration Register (SMICFG)148
Tab. 152. SMI Settling Time Register (SMIST) (Address $0043)149
Tab. 153. SMIST Register Field Descriptions149
Tab. 154. SP[3:0]149
SMI Settling Time Register (SMIST)149
Tab. 155. ISD[3:0]150
Parameter Registers (PARAM0 to PARAM63)150
Tab. 156. Parameter Registers (PARAM0 to PARAM31) (Addresses $0050 - $006F)151
Tab. 157. Parameter Registers (PARAM32 to PARAM63) (Addresses $0070 - $008F)151
Tab. 158. Random Access Memory Registers (RAM0 to RAM255) (Addresses $0090 - $00FF)151
Tab. 159. Parameter Registers (RAM256 to RAM511) (Addresses $0100 - $028F)151
Random Access Memory (RAM0 to RAM511)151
System Integration Module (SIM)152
SIM Reset Exit154
SIM MCU Mode Control155
Tab. 160. SIM Reset Status Register (SIMRS) (Address $1800)156
Tab. 161. SIMRS Register Field Descriptions156
SIM Register Descriptions156
SIM Reset Status Register (SIMRS)156
Tab. 162. SIM Control Register (SIMC) (Address $1801) . 157 Tab. 163. SIMC Register Field Descriptions157
SIM Control Register (SIMC)157
SIM Option 1 Register (SIMOPT1)157
Tab. 164. SIM Option 1 Register (SIMOPT1) (Address $1802)158
Tab. 165. SIMOPT1 Register Field Descriptions158
Tab. 166. SIM Option 2 Register (SIMOPT2) (Address $1803)159
Tab. 167. SIMOPT2 Field Descriptions159
SIM Option 2 Register (SIMOPT2)159
Tab. 168. SIM Part ID High Register (SIMPID1) (Address $1806)160
Tab. 169. SIM Part ID Low Register (SIMPID2) (Address $1807)160
Tab. 170. SIMPID1/SIMPID2 Register Field Descriptions160
Tab. 171. SIM Stop Exit Status Register (SIMSES) (Address $180D)160
SIM Part ID High and Low Byte Registers (SIMPID1/SIMPID2)160
SIM Stop Exit Status Register (SIMSES)160
Tab. 172. SIMSES Register Field Descriptions161
Tab. 173. SIM Oscillator Trim Register (SIMOTRM) (Address $180E)161
SIM Oscillator Trim Register (SIMOTRM)161
Tab. 174. SIMOTRM Register Field Descriptions162
Power Management Controller (PMC) Module162
PMC State Transitions164
PMC Low Voltage Detection Transitions165
PMC Register Descriptions165
PMC Real-Time-Interrupt Status and Control Register (SRTISC)165
Tab. 176. SRTISC Register Field Descriptions166
PMC Status and Control 1 Register (SPMSC1)166
Tab. 177. PMC Status and Control 1 Register (SPMSC1) (Address $1809)167
Tab. 178. SPMSC1 Register Field Descriptions167
Tab. 179. PMC Status and Control 2 Register (SPMSC2) (Address $180A)168
Tab. 180. SPMSC2 Register Field Descriptions168
Tab. 181. PMC Status and Control 3 Register (PMCSC3) (Address $180C)168
PMC Status and Control 2 Register (SPMSC2)168
PMC Status and Control 3 Register (PMCSC3)168
Tab. 182. PMCSC3 Register Field Descriptions169
Flash Memory Controller (FMC) Module169
Flash Controller General Items169
Tab. 183. Program and Erase Times170
FMC Program and Erase Times170
FMC Program and Erase Command Execution170
FMC Burst Program Execution171
FMC Memory Access Errors173
FMC Block Protection174
FMC Vector Redirection175
FMC Security175
Tab. 184. FMC Clock Divider Register (FCDIV) (Address $1820)177
Tab. 185. FCDIV Register Field Descriptions177
Tab. 186. FMC Clock Divider Register Settings177
FMC Register Descriptions177
FMC Clock Divider Register (FCDIV)177
Tab. 187. FMC Option Registers (FOPT) (Address $1821)178
Tab. 188. FMC Option Registers (NVOPT) (Address $FFBF)178
FMC Option Registers (FOPT and NVOPT)178
Tab. 189. FOPT and NVOPT Register Field Descriptions . 178 Tab. 190. FMC Configuration Registers (FCNFG) (Address $1823)179
Tab. 191. FCNFG Register Field Descriptions179
Tab. 192. Flash Protection Register (FPROT) (Address $1824)179
Tab. 193. Flash Protection Register (NVPROT) (Address $FFBD)179
FMC Configuration Registers (FCNFG)179
Flash Protection Registers (FPROT and NVPROT)179
Tab. 194. FPROT and NVPROT Register Field Descriptions180
Tab. 195. FMC Status Register (FSTAT) (Address $1825)180
Tab. 196. FMC Status Register (FSTAT) (Address $1825)180
Tab. 197. FSTAT Register Field Descriptions180
FMC Status Register (FSTAT)180
Tab. 198. FMC Command Register (FCMD) (Address $1826)181
Tab. 199. FCMD Register Field Descriptions181
Tab. 200. FCMD Available Flash Commands181
FMC Command Register (FCMD)181
Free Running Counter (FRC) Module182
Clearing or Halting the FRC182
Tab. 201. FRC Status and Control Register (FRCCR) (Address $1880)183
Tab. 202. FRCCR Register Field Descriptions183
Free Running Counter Register Descriptions183
FRC Status and Control Register (FRCCR)183
Tab. 203. FRC Timer High Register (FRCTIMERH) (Address $1881)184
Tab. 204. FRC Timer Low Register (FRCTIMERL) (Address $1882)184
Tab. 205. FRCTIMERH/L Register Field Descriptions184
Tab. 206. FRC Compare High Register (FRCCOMP2) (Address $1883)184
FRC Timer High and Low Registers (FRCTIMERH/L)184
FRC Compare High and Low Registers (FRCCOMP2/1)184
Tab. 207. FRC Compare Low Register (FRCCOMP1) (Address $1884)185
Tab. 208. FRCCOMP2/1 Register Field Descriptions185
Other MCU Resources185
Tab. 209. ADC10 Channel Assignments186
Pressure Measurement186
Temperature Measurements187
Voltage Measurements187
Internal Band Gap187
External Voltages187
Optional Acceleration Measurements187
Optional Battery Condition Check188
Measurement Firmware189
Battery Charge Consumption Modeling190
Standby Current190
Measurement Events190
Transmission Events191
Total Consumption191
Application Information192
Tab. 210. Revision History195
Revision History195
Legal Information198
Table of Contents200
Tab. 175. PMC Real-Time-Interrupt Status and Control205

NXP Semiconductors UM11227 - Page 163

Table of Contents