NXP Semiconductors UM11227 - Page 203

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
203 / 205
Contents
1 Introduction ......................................................... 1
1.1 Purpose ..............................................................1
1.2 Audience ............................................................1
2 General description ............................................ 1
3 Features and benefits .........................................1
4 Configuration options .........................................2
4.1 Electronic encoding - "CodeF" ...........................2
4.2 Electronic encoding - "CodeH" .......................... 3
4.3 Device identification ...........................................3
4.4 Definition of signal ranges ................................. 4
4.5 Memory resource usage ....................................5
5 Marking .................................................................5
5.1 Exterior markings ...............................................5
6 Block diagram ..................................................... 6
7 Pinning information ............................................ 7
7.1 Pinout .................................................................7
7.2 Pin description ................................................... 7
7.3 Orientation ....................................................... 10
8 Central processing unit ....................................10
8.1 Introduction ...................................................... 10
8.2 Features ...........................................................10
8.3 Programmer’s model and CPU registers ......... 11
8.3.1 Accumulator (A) ............................................... 11
8.3.2 Index register (H:X) ......................................... 12
8.3.3 Stack pointer (SP) ........................................... 12
8.3.4 Program counter (PC) ..................................... 12
8.3.5 Condition code register (CCR) ........................ 13
8.4 Addressing modes ........................................... 14
8.4.1 Inherent addressing mode (INH) ..................... 14
8.4.2 Relative addressing mode (REL) .....................14
8.4.3 Immediate addressing mode (IMM) ................. 14
8.4.4 Direct addressing mode (DIR) ......................... 15
8.4.5 Extended addressing mode (EXT) ...................15
8.4.6 Indexed addressing mode ............................... 15
8.4.6.1 Indexed, no offset (IX) .....................................15
8.4.6.2 Indexed, no offset with post increment (IX+) ....15
8.4.6.3 Indexed, 8-bit offset (IX1) ................................ 15
8.4.6.4 Indexed, 8-bit offset with post increment
(IX1+) ............................................................... 15
8.4.6.5 Indexed, 16-bit offset (IX2) .............................. 15
8.4.6.6 SP-Relative, 8-bit offset (SP1) .........................16
8.4.6.7 SP-Relative, 16-bit offset (SP2) .......................16
8.5 Special operations ........................................... 16
8.5.1 Reset sequence ...............................................16
8.5.2 Interrupt sequence ...........................................16
8.5.3 WAIT mode operation ......................................17
8.5.4 STOP mode operation .....................................17
8.5.5 BGND instruction ............................................. 18
8.6 HCS08 instruction set summary ...................... 18
8.6.1 Instruction set summary nomenclature ............ 18
8.6.2 Operators ......................................................... 18
8.6.3 CPU registers .................................................. 18
8.6.4 Memory and addressing .................................. 18
8.6.5 Condition code register (CCR) bits ..................19
8.6.6 CCR activity notation ....................................... 19
8.6.7 Machine coding notation ..................................19
8.6.8 Source form ..................................................... 19
8.6.9 Address modes ................................................20
9 Development support ....................................... 31
9.1 Introduction ...................................................... 31
9.1.1 Features ...........................................................31
9.2 Background debug controller (BDC) ................ 32
9.2.1 BKGD/PTA4 pin description ............................ 32
9.2.2 Communication details .................................... 33
9.2.3 BDC commands .............................................. 35
9.2.3.1 Coding structure nomenclature ........................35
9.2.4 BDC hardware breakpoint ............................... 37
9.3 Register definition ............................................38
9.3.1 BDC registers and control bits .........................38
9.3.2 BDC status and control register (BDCSCR) .....38
9.3.3 BDC breakpoint match register (BDCBKPT) ....39
9.3.4 System background debug force reset
register (SBDFR) ............................................. 40
10 Functional description ......................................40
10.1 Register information .........................................40
10.1.1 Register map ................................................... 40
10.1.2 Register description format ..............................47
10.2 Interrupts ..........................................................48
10.2.1 Interrupt stack frame ........................................49
10.2.2 Vector summary .............................................. 50
10.3 Interrupt service routines ................................. 50
10.4 Low-Voltage Detect (LVD) System .................. 51
10.4.1 Power-on reset operation ................................ 51
10.4.2 LVD reset operation ........................................ 51
10.4.3 LVD interrupt operation ................................... 52
10.4.4 Low-Voltage Warning (LVW) ........................... 52
10.5 System clock control ........................................52
10.6 Keyboard interrupts ......................................... 52
10.7 Real-time interrupt ........................................... 52
10.8 Modes of operation ..........................................53
10.8.1 Features ...........................................................53
10.8.2 RUN mode .......................................................53
10.8.3 WAIT mode ......................................................53
10.8.4 ACTIVE BACKGROUND mode ....................... 53
10.8.5 STOP Modes ................................................... 54
10.8.5.1 STOP1 Mode ...................................................54
10.8.5.2 STOP4 LVD enabled in STOP mode ...............54
10.8.5.3 Active BDM enabled in STOP mode ................56
10.8.5.4 MCU on-chip peripheral modules in STOP
modes .............................................................. 56
10.8.5.5 RFM module in STOP modes ......................... 57
10.8.5.6 P-cell in STOP modes .....................................58
10.8.5.7 Optional g-cell in STOP modes ....................... 58
10.9 Memory ............................................................ 58
10.9.1 Memory map - parts delivered without
firmware in flash .............................................. 58
10.10 Clock distribution ............................................. 59
10.11 Reset, interrupts and system configuration ......60
10.11.1 Features ...........................................................60
10.11.2 MCU reset ....................................................... 61
10.11.3 Computer Operating Properly (COP)
Watchdog .........................................................61