Agilent Technologies 93000 SOC Series - Page 125

Lesson 1 – Analog Modules
125
Master Clock Distribution in MCA
One master clock source can be selected for one MCA module, and
the selected master clock is distributed to all the units, and is
used by AWGs and digitizers. Each unit has its own timing
generator, so a different sampling rate (Fs) can be set for each
unit.
For details of the relationship between the sampling rate (Fs) and
the master clock period in each AWG or digitizer, see the manual,
System Reference.
Timing Generator
Fs
1
Unit 1
Fs
2
Unit 2
Fs
3
Unit 3
Fs
4
Unit 4
Fs
5
Unit 5
Fs
6
Unit 6
Fs
7
Unit 7
Fs
8
Unit 8
1/N
1
• Sampling period (1/Fs) is a multiple of MCLK period
• Different Fs in each unit allowed:
MCLK-to-Fs frequency divider (N) in each unit
• One MCLK source for 8 units
1/N
2
1/N
3
1/N
4
1/N
5
1/N
6
1/N
7
1/N
8
One Master Clock (MCLK) source
in the selected clock domain
Multi-site Baseband Analog Module