Agilent Technologies 93000 SOC Series - Page 148

Lesson 3 – Synchronization of Analog Modules
148
Table 25 Parameters of 4.1G AWG Trigger-to-Signal Delay
In the above tables, “Clock Domain” column means which clock domain is
used for the analog module. Digital clock domain means the same master
clock is used between the trigger signal from digital channel and analog
module. “1 master clock period” means one period of the master clock used
for the analog module. “Trigger-to-Signal Delay” consists of the default
fixed trigger delay time and timing accuracy that is shown in “()”. You can
also add an additional delay time to the trigger delay time, however the spec-
ified value will be rounded according to the resolution determined for each
analog module. Start timing of the analog module varies within the range
shown in the “Trigger-to-Signal Delay” column even if the test is done
under the same conditions, as the figure below.
Sampling Frequency (Fs) X [s] Y [s]
4.00 GHz < Fs ≤ 4.10 GHz 14.34 x 10
-9
+ 223.5/Fs 0.6 x 10
-9
+ 1/(32 × Fmclk)
3.15 GHz < Fs ≤ 4.00 GHz 14.34 x 10
-9
+ 223.5/Fs 200 MHz ≤ Fmclk < 250 MHz:
0.6 x 10
-9
+ 1/(32 × Fmclk)
250 MHz ≤ Fmclk ≤ 500 MHz:
0.6 x 10
-9
+ 1/(16 × Fmclk)
Fmclk: Master Clock Frequency
(e.g. Y = 0.725 ×10
-9
@Fmclk = 500 MHz)
2.00 GHz < Fs ≤ 3.15 GHz 14.34 x 10
-9
+ 219.5/Fs
1.95 GHz < Fs ≤ 2.00 GHz 14.54 x 10
-9
+ 217.0/Fs
1.00 GHz < Fs ≤ 1.95 GHz 14.54 x 10
-9
+ 213.0/Fs
900 MHz < Fs ≤ 1.95 GHz 14.64 x 10
-9
+ 211.75/Fs
500 MHz < Fs ≤ 900 MHz 14.64 x 10
-9
+ 207.75/Fs
250 MHz < Fs ≤ 500 MHz 14.84 x 10
-9
+ 207.125/Fs
125 MHz < Fs ≤ 250 MHz 16.34 x 10
-9
+ 206.8125/Fs
62.5 MHz < Fs ≤ 125 MHz 16.84 x 10
-9
+ 206.65625/Fs
31.25 MHz < Fs ≤ 62.5 MHz 16.94 x 10
-9
+ 206.57813/Fs
25.0 MHz < Fs ≤ 31.25 MHz 17.44 x 10
-9
+ 206.53906/Fs