Agilent Technologies 93000 SOC Series - Page 618

Appendix D
618
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Lower Sampling
Comparators
(4-Bit)
Lower Encoder
(4-Bit)
Lower Data
Latch
Lower Sampling
Comparators
(4-Bit)
Lower Encoder
(4-Bit)
Upper Sampling
Comparators
(4-Bit)
Upper Encoder
(4-Bit)
Upper Data
Latch
Clock
Generator
OE
D1(LSB)
D2
D3
D4
D5
D6
D7
D8(MSB)
CLK
REFB
REFT
REFBS
AGND
AGND
ANALOG IN
V
DDA
REFTS
270 Ω
NOM
80 Ω
NOM
320 Ω
NOM
Resistor
Reference
Divider
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
V
DDA
AGND
ANALOG IN
EQUIVALENT OF EACH DIGITAL INPUT
V
DDD
DGND
OE, CLK
EQUIVALENT OF EACH DIGITAL OUTPUT
V
DDD
DGND
D1–D8