ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-1
Chapter 3
Memory Management Unit
This chapter describes the Memory Management Unit (MMU). It contains the following
sections:
• About the MMU on page 3-2
• Address translation on page 3-5
• MMU faults and CPU aborts on page 3-21
• Domain access control on page 3-24
• Fault checking sequence on page 3-26
• External aborts on page 3-29
• TLB structure on page 3-31.
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