Memory Management Unit
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-27
• Translation faults
• Domain faults
• Permission faults on page 3-28.
3.5.1 Alignment faults
If alignment fault checking is enabled (the A bit in CP15 c1 is set), the MMU generates
an alignment fault on any data word access if the address is not word-aligned, or on any
halfword access if the address is not halfword-aligned, irrespective of whether the
MMU is enabled or not. An alignment fault is not generated on any instruction fetch or
any byte access.
Note
If an access generates an alignment fault, the access sequence aborts without reference
to other permission checks.
3.5.2 Translation faults
There are two types of translation fault:
Section A section translation fault is generated if the level one descriptor is
marked as invalid. This happens if bits [1:0] of the descriptor are both 0.
Page A page translation fault is generated if the level one descriptor is marked
as invalid. This happens if bits [1:0] of the descriptor are both 0.
3.5.3 Domain faults
There are two types of domain fault:
Section The level one descriptor holds the four-bit domain field, which selects
one of the 16 two-bit domains in the domain access control register. The
two bits of the specified domain are then checked for access permissions
as described in Table 3-12 on page 3-24. The domain is checked when the
level one descriptor is returned.
Page The level one descriptor holds the four-bit domain field, which selects
one of the 16 two-bit domains in the domain access control register. The
two bits of the specified domain are then checked for access permissions
as described in Table 3-12 on page 3-24. The domain is checked when the
level one descriptor is returned.
If the specified access is either no access (00), or reserved (10), then either a section
domain fault or page domain fault occurs.
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