Atmel AVR XMEGA AU series User Manual

214
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit 2 – FDF: Fault Detect Flag
This flag is set when a fault detect condition is detected; i.e., when an event is detected on one
of the event channels enabled by FDEVMASK. This flag is cleared by writing a one to its bit
location.
• Bit 1 – DTHSBUFV: Dead-time High Side Buffer Valid
If this bit is set, the corresponding DT buffer is written and contains valid data that will be copied
into the DTLS register on the next UPDATE condition. If this bit is zero, no action will be taken.
The connected timer/counter unit’s lock update (LUPD) flag also affects the update for dead-
time buffers.
• Bit 0 – DTLSBUFV: Dead-time Low Side Buffer Valid
If this bit is set, the corresponding DT buffer is written and contains valid data that will be copied
into the DTHS register on the next UPDATE condition. If this bit is zero, no action will be taken.
The connected timer/counter unit's lock update (LUPD) flag also affects the update for dead-
time buffers.
16.7.5 DTBOTH – Dead-time Concurrent Write to Both Sides
• Bit 7:0 – DTBOTH: Dead-time Both Sides
Writing to this register will update the DTHS and DTLS registers at the same time (i.e., at the
same I/O write access).
16.7.6 DTBOTHBUF – Dead-time Concurrent Write to Both Sides Buffer register
• Bit 7:0 – DTBOTHBUF: Dead-time Both Sides Buffer
Writing to this memory location will update the DTHSBUF and DTLSBUF registers at the same
time (i.e., at the same I/O write access).
16.7.7 DTLS – Dead-time Low Side register
Bit 76543210
+0x06 DTBOTH[7:0] DTBOTH
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
+0x07 DTBOTHBUF[7:0] DTBOTHBUF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
+0x08 DTLS[7:0] DTLS
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

Atmel AVR XMEGA AU series Specifications

General

Brand	Atmel
Model	AVR XMEGA AU series
Category	Microcontrollers
Language	English