33
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit: 4 – RSTDISBL: External Reset Disable
This fuse can be programmed to disable the external reset pin functionality. When this is done
pulling the pin low will not cause an external reset. A reset is required before this bit will be read
correctly after it is changed.
• Bit 3:2 – STARTUPTIME[1:0]: Start-up time
These fuse bits can be used to set at a programmable timeout period from all reset sources are
released until the internal reset is released from the delay counter. A reset is required before
these bits will be read correctly after they are changed.
The delay is timed from the 1kHz output of the ULP oscillator. Refer to ”Reset Sequence” on
page 114 for details.
• Bit 1 – WDLOCK: Watchdog Timer Lock
The WDLOCK fuse can be programmed to lock the watchdog timer configuration. When this
fuse is programmed the watchdog timer configuration cannot be changed, and the ENABLE bit
in the watchdog CTRL register is automatically set at reset and cannot be cleared from the appli-
cation software. The WEN bit in the watchdog WINCTRL register is not set automatically and
needs to be set from software. A reset is required before this bit will be read correctly after it is
changed.
• Bit 0 – JTAGEN: JTAG Enabled
This fuse controls whether or not the JTAG interface is enabled.
When the JTAG interface is disabled all access through JTAG is prohibited, and the device can
be accessed using only the program and debug interface (PDI). The JTAGEN fuse is available
on devices with JTAG interface. A reset is required before this bit will be read correctly after it is
changed.
Table 4-4. Start-up time.
STARTUPTIME[1:0] 1kHz ULP Oscillator Cycles
00 64
01 4
10 Reserved
11 0
Table 4-5. Watchdog timer lock.
WDLOCK Description
0 Watchdog timer locked for modifications
1 Watchdog timer not locked
Table 4-6. JTAG Enable
JTAGEN Description
0 JTAG enabled
1 JTAG disabled
To Next Page
Loading...
Need help?
General
