Atmel AVR XMEGA AU series

394
8331B–AVR–03/12
Atmel AVR XMEGA AU
29.10.7 CH0DATAL – Channel 0 Data Register Low
29.10.7.1 Right-adjusted
• Bit 7:0 – CHDATA[7:0]: Conversion Data Register Channel 0, Eight lsbs
These bits are the eight lsbs of the 12-bit value to convert to channel 0 in right-adjusted mode.
29.10.7.2 Left-adjusted
• Bit 7:4 – CHDATA[3:0]: Conversion Data Register Channel 0, Four lsbs
These bits are the four lsbs of the 12-bit value to convert to channel 0 in left-adjusted mode.
• Bit 3:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
29.10.8 CH1DATAH – Channel 1 Data Register High
29.10.8.1 Right-adjusted
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:0 – CHDATA[11:8]: Conversion Data Register Channel 1, Four msbs
These bits are the four msbs of the 12-bit value to convert to channel 1 in right-adjusted mode.
29.10.8.2 Left-adjusted
• Bit 7:0 – CHDATA[11:4]: Conversion Data Register Channel 1, Eight msbs
These bits are the eight msbs of the 12-bit value to convert to channel 1 in left-adjusted mode.
Bit 76543210
Right-adjust
+0x18
CHDATA[7:0]
Left-adjust CHDATA[3:0] – – – –
Right-adjust Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Left-adjust Read/Write R/W R/W R/W R/W R R R R
Right-adjustInitial Value 00000000
Left-adjustInitial Value 00000000
Bit 76543210
Right-adjust
+0x1B
– – – – CHDATA[11:8]
Left-adjust CHDATA[11:4]
Right-adjust Read/Write R R R R R/W R/W R/W R/W
Left-adjust Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Right-adjustInitial Value 00000000
Left-adjustInitial Value 00000000