Atmel AVR XMEGA AU series

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8331B–AVR–03/12
Atmel AVR XMEGA AU
6.2 Overview ..........................................................................................................71
6.3 Events ..............................................................................................................72
6.4 Event Routing Network ....................................................................................74
6.5 Event Timing ....................................................................................................76
6.6 Filtering ............................................................................................................76
6.7 Quadrature Decoder ........................................................................................76
6.8 Register Description ........................................................................................78
6.9 Register Summary ...........................................................................................82
7 System Clock and Clock Options ......................................................... 83
7.1 Features ..........................................................................................................83
7.2 Overview ..........................................................................................................83
7.3 Clock Distribution .............................................................................................85
7.4 Clock Sources .................................................................................................85
7.5 System Clock Selection and Prescalers ..........................................................87
7.6 PLL with 1x-31x Multiplication Factor ..............................................................88
7.7 DFLL 2MHz and DFLL 32MHz ........................................................................89
7.8 PLL and External Clock Source Failure Monitor ..............................................90
7.9 Register Description – Clock ...........................................................................92
7.10 Register Description – Oscillator .....................................................................96
7.11 Register Description – DFLL32M/DFLL2M ....................................................101
7.12 Register Summary - Clock .............................................................................104
7.13 Register Summary - Oscillator .......................................................................104
7.14 Register Summary - DFLL32M/DFLL2M .......................................................104
7.15 Oscillator Failure Interrupt Vector Summary .................................................104
8 Power Management and Sleep Modes ............................................... 105
8.1 Features ........................................................................................................105
8.2 Overview ........................................................................................................105
8.3 Sleep Modes ..................................................................................................105
8.4 Power Reduction Registers ...........................................................................107
8.5 Minimizing Power Consumption ....................................................................107
8.6 Register Description – Sleep .........................................................................109
8.7 Register Description – Power Reduction .......................................................109
8.8 Register Summary – Sleep ............................................................................112
8.9 Register Summary – Power Reduction .........................................................112
9 Reset System ....................................................................................... 113