Atmel AVR XMEGA AU series

ii
8331B–AVR–03/12
Atmel AVR XMEGA AU
4.12 Device ID and Revision ...................................................................................25
4.13 JTAG Disable ..................................................................................................25
4.14 I/O Memory Protection .....................................................................................25
4.15 Register Description – NVM Controller ............................................................26
4.16 Register Descriptions – Fuses and Lock bits ..................................................31
4.17 Register Description – Production Signature Row ..........................................37
4.18 Register Description – General Purpose I/O Memory .....................................46
4.19 Register Description – External Memory .........................................................46
4.20 Register Descriptions – MCU Control ..............................................................47
4.21 Register Summary - NVM Controller ...............................................................51
4.22 Register Summary - Fuses and Lockits ...........................................................51
4.23 Register Summary - Production Signature Row ..............................................52
4.24 Register Summary – General Purpose I/O Registers ......................................53
4.25 Register Summary – MCU Control ..................................................................53
4.26 Interrupt Vector Summary – NVM Controller ...................................................53
5 DMAC - Direct Memory Access Controller .......................................... 54
5.1 Features ..........................................................................................................54
5.2 Overview ..........................................................................................................54
5.3 DMA Transaction .............................................................................................55
5.4 Transfer Triggers .............................................................................................56
5.5 Addressing .......................................................................................................56
5.6 Priority Between Channels ..............................................................................56
5.7 Double Buffering ..............................................................................................57
5.8 Transfer Buffers ...............................................................................................57
5.9 Error detection .................................................................................................57
5.10 Software Reset ................................................................................................57
5.11 Protection ........................................................................................................57
5.12 Interrupts .........................................................................................................58
5.13 Register Description – DMA Controller ............................................................59
5.14 Register Description – DMA Channel ..............................................................61
5.15 Register Summary – DMA Controller ..............................................................70
5.16 Register Summary – DMA Channel ................................................................70
5.17 DMA Interrupt Vector Summary ......................................................................70
6 Event System ......................................................................................... 71
6.1 Features ..........................................................................................................71