Atmel AVR XMEGA AU series

i
8331B–AVR–03/12
Atmel AVR XMEGA AU
Table Of Contents
1 About the Manual ..................................................................................... 2
1.1 Reading the Manual ..........................................................................................2
1.2 Resources .........................................................................................................2
1.3 Recommended Reading ....................................................................................2
2 Overview ................................................................................................... 3
3 AVR CPU .................................................................................................. 7
3.1 Features ............................................................................................................7
3.2 Overview ............................................................................................................7
3.3 Architectural Overview .......................................................................................7
3.4 ALU - Arithmetic Logic Unit ...............................................................................8
3.5 Program Flow ....................................................................................................9
3.6 Instruction Execution Timing .............................................................................9
3.7 Status Register ................................................................................................10
3.8 Stack and Stack Pointer ..................................................................................10
3.9 Register File ....................................................................................................11
3.10 RAMP and Extended Indirect Registers ..........................................................12
3.11 Accessing 16-bit Registers ..............................................................................13
3.12 Configuration Change Protection ....................................................................13
3.13 Fuse Lock ........................................................................................................14
3.14 Register Descriptions ......................................................................................15
3.15 Register Summary ...........................................................................................19
4 Memories ................................................................................................ 20
4.1 Features ..........................................................................................................20
4.2 Overview ..........................................................................................................20
4.3 Flash Program Memory ...................................................................................21
4.4 Fuses and Lockbits ..........................................................................................22
4.5 Data Memory ...................................................................................................23
4.6 Internal SRAM .................................................................................................23
4.7 EEPROM .........................................................................................................23
4.8 I/O Memory ......................................................................................................24
4.9 External Memory .............................................................................................24
4.10 Data Memory and Bus Arbitration ...................................................................24
4.11 Memory Timing ................................................................................................25