7210 SAS-MXP, R6, R12, S, SX, T BASIC SYSTEM
CONFIGURATION GUIDE RELEASE 22.9.R1
System management
7210 SAS platformsSynchronization options
T S 1/10GE R6 R12
Mxp
15
Sx 1/10GE
15
Sx 10/100GE
15
PTP end-to-end (E2E) transparent
clock
✓ ✓
BITS
✓
22
✓
23
✓
23
✓
1pps and 10MHz interfaces
✓
24
✓
24
✓
24
✓
24
6.5.3 Synchronization Status Messages
Synchronization Status Messages (SSM) are supported on devices that support Synchronous Ethernet.
SSM allows the synchronization distribution network to determine the quality level of the clock sourcing
a specific synchronization trail and also allows a network element to select the best of multiple input
synchronization trails. SSMs are defined for various transport protocols (including SONET/SDH, T1/E1,
and Synchronous Ethernet), for interaction with office clocks (such as BITS or SSUs) and embedded
network element clocks.
SSM allows equipment to autonomously provision and reconfigure (by reference switching) their
synchronization references, while helping to avoid the creation of timing loops. These messages are
particularly useful for synchronization re-configurations when timing is distributed in both directions around
a ring.
6.5.4 DS1 signals
DS1 signals can carry the quality level value of the timing source information using the SSM that is
transported within the 1544 kb/s signal Extended Super Frame (ESF) Data Link (DL), as described in ITU-
T Recommendation G.704. No such provision is extended to SF formatted DS1 signals.
The format of the ESF DL messages is 0xxx xxx0 1111 1111, with the rightmost bit transmitted first. The 6
bits denoted by xxx xxx contain the message; some of these messages are reserved for synchronization
messaging. It takes 32 frames (4 ms) to transmit all 16 bits of a complete DL.
6.5.5 E1 signals
E1 signals can carry the quality level value of the timing source information using the SSM, as described in
ITU-T Recommendation G.704.
One of the Sa4 to Sa8 bits is allocated for SSMs; choosing the Sa bit that carries the SSM is user-
configurable. To prevent ambiguities in pattern recognition, it is necessary to align the first bit (San1) with
frame 1 of a G.704 E1 multiframe.
15
Operating in standalone mode
22
Supports two BITS ports configured as input or output
23
Supports one BITS port (that is, BITS1), configured as input or output
24
1pps and 10MHz output available only when PTP is used as a reference for the system clock
3HE 18197 AAAB TQZZA
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Use subject to Terms available at: www.nokia.com/terms/.
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