7210 SAS-MXP, R6, R12, S, SX, T BASIC SYSTEM
CONFIGURATION GUIDE RELEASE 22.9.R1
System management
Note:
• The 7210 SAS-Mxp, 7210 SAS-R6, 7210 SAS-R12, 7210 SAS-Sx 1/10GE, 7210 SAS-Sx
10/100GE 64SFP+ 4QSFP28, and 7210 SAS-T support only one-step timeTransmitter port
operation.
• All platforms can operate timeReceiver ports that receive PTP messages from a one-step or
two-step timeTransmitter port.
During startup, the PTP timeReceiver clock receives synchronization messages from the PTP
timeTransmitter clock before a network delay calculation is made. Before any delay calculation, the delay is
assumed to be zero. A drift compensation is activated after a number of synchronization message intervals
occur. The expected interval between the reception of synchronization messages is user-configurable.
The following figure shows the basic synchronization timing computation between the PTP timeReceiver
clock and PTP best timeTransmitter; the offset of the timeReceiver clock is shown referenced to the best
timeTransmitter signal during startup.
Figure 26: PTP timeReceiver clock and timeTransmitter clock synchronization timing computation
When the IEEE 1588v2 standard is used for distribution of a frequency reference, the timeReceiver
calculates a message delay from the timeTransmitter to the timeReceiver based on the timestamps
exchanged. A sequence of these calculated delays contains information about the relative frequencies
of the timeTransmitter clock and timeReceiver clock, but also includes a noise component related to the
PDV experienced across the network. The timeReceiver must filter the PDV effects to extract the relative
frequency data and then adjust the timeReceiver frequency to align with the timeTransmitter frequency.
When the IEEE 1588v2 standard is used for distribution of time, the 7210 SAS calculates the offset
between the 7210 SAS time base and the external timeTransmitter clock time base based on the four
timestamps exchanged. The 7210 SAS determines the offset adjustment, and between these adjustments,
it maintains the progression of time using the frequency from the central clock of the node. This allows time
to be maintained using a Synchronous Ethernet input source even if the IEEE 1588v2 communications fail.
When using IEEE 1588v2 for time distribution, the central clock should, at a minimum, have the PTP input
reference enabled.
3HE 18197 AAAB TQZZA
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