NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Table 79. LFCTL3 register field descriptions
Field Description
7
LFDO
LFDO – LF Detector Output
This read-only bit follows the bit slicer output signal that goes high during the presence of a carrier. It may
change at any time.
0 = LF detector output low (no signal above threshold); Result of power-on reset. Existing state remains
after all other types of reset.
1 = LF detector output high (received signal above threshold)
6
TOGMOD
TOGMOD – LFR Mode Toggle
This read/write bit enables the toggling of the CARMOD bit at each new LFON sequence. Reset clears this
bit. Therefore the reception chain will alternately look for a carrier frame or for a data frame.
0 = CARMOD bit does not change and determines detector mode; Result of power on or LFR reset. Existing
state remains after all other reset types.
1 = CARMOD bit will be toggled every LFON detection sequence, starting by CARMOD selection.
5:4
SYNC[1:0]
SYNC[1:0] – LF Synchronization Patter Selection
The two bits SYNC[1:0] selects the type of SYNC pattern. Reset presets these bits to the 11 (9T SYNC)
option. Compatible with preamble consisting of minimum 2 ms Manchester data to allow for proper
averaging filter operation.
0 0 = For factory test purposes, not intended for use in any application.
0 1 = 6T SYNC pattern
1 0 = 7.5T SYNC pattern
1 1 = 9T SYNC pattern; Result of power on or LFR reset. Existing state remains after all other reset types.
3:0
LFCDTM[3:0]
LFCDTM[3:0] – LF Carrier Detect Time
The 4 bits LFCDTM[3:0] select the length of time which the LFR input detector must detect a carrier before
validating it. In carrier mode (CARMOD = 1), if the carrier is active for at least the time selected by the
LFCDTM[3:0] bits and the LFCC counter value is reached, the LFCDF flag in the LFS register will be set;
and if the LFCDIE control bit is also set, the MCU will be interrupted (wake-up).
In the data receive mode (CARMOD = 0) the LFCDTM[3:0] bits select the length of time which the LFR input
detector must detect a carrier before the effective receive chain is powered on. Once the carrier has been
validated the LFCDTM[3:0] bits ignored during the decode of the rest of the data.
0 0 1 0 = Result of power on or LFR reset. Existing state remains after all other reset types.
See Table 80 for additional states.
Table 80. LF carrier and data detect states
Carrier detect Data detect
LFCDTM[3:0] Clock Cycles ~ Time µs Clock Cycles ~ Time µs
0 0 0 0 8 64 8 64
0 0 0 1 16 128 8 64
0 0 1 0 32 256 8 64
0 0 1 1 64 512 8 64
0 1 0 0 128 1024 8 64
0 1 0 1 256 2048 8 64
0 1 1 0 512 4096 8 64
0 1 1 1 1024 8192 8 64
1 0 0 0 8 64 8 64
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