0200
08
0000
03
0000
04
C0007
0000
05
(012)
CNTR 0007 0001
SV: CIO 0001
157
When inputting the CNTR(012) instruction with mnemonics, first enter the incre-
ment input (II), then the decrement input (DI), the reset input (R), and finally the
CNTR(012) instruction. When entering with the ladder diagrams, first input the
increment input (II), then the CNTR(012) instruction, the decrement input (DI),
and finally the reset input (R).
Changes in II and DI execution conditions, the Completion Flag, and the PV are
illustrated below starting from part way through CNTR(012) operation (i.e.,
when reset, counting begins from zero). PV line height is meant only to indicate
changes in the PV and not absolute values.
Execution condition
on increment (II)
Execution condition
on decrement (DI)
ON
OFF
ON
OFF
Completion Flag
ON
OFF
PV
SV
SV – 1
SV – 2
0001
0000 0000
SV
SV – 1
SV – 2
Precautions SV must be BCD between 0000 and 9999.
Counter numbers are as shown in the following table. Each counter number can
be used to define only one counter instruction unless the counters are never ac-
tive simultaneously.
PC Counter numbers
CV500 or CVM1-CPU01-EV2 C0000 through C0511
CV1000, CV2000, or CVM1-CPU11/21-EV2 C0000 through C1023
Note: Refer to page 115 for general precautions on operand data areas.
Flags ER (A50003): Content of *DM word is not BCD when set for BCD.
Content of S (SV) is not BCD.
Example The counter in the following example will count up when CIO 000003 changes
from OFF to ON and will count down when CIO 000004 changes from OFF to
ON. If CIO 000005 turns ON, the PV will be reset to 0000 and counting will be
disabled until CIO 000005 turns OFF.
Address Instruction Operands
00000 LD 000003
00001 LD 000004
00002 LD 000005
00003 CNTR(012) 0007
0001
00004 LD NOT C0007
00005 OUT 020008
Timer and Counter Instructions Section 5-13
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